Multiphase interleaving buck converters are widely used in today's industrial point-of-load (POL) converters, especially the microprocessor voltage regulators (VRs). The issue of today's multiphase interleaving buck converters is the conflict between the high efficiency and the fast transient in the phase inductor design. In 2000, P. Wong proposed the multiphase coupledinductor buck converter to solve this issue. With the phase inductors coupled together, the coupled-inductor worked as a nonlinear inductor due to the phase-shifted switching network, and the coupled-inductor has different equivalent inductances during steady-state and transient. One the one hand, the steady state inductance is increased due to coupling and the efficiency of the multiphase coupled-inductor buck converter is increased; on the other hand, the transient inductance is reduced and the transient performance of the multiphase coupled-inductor buck is improved. After that, many researches have investigated the multiphase coupled-inductor buck converters in different aspects. However, there are still many challenges in this area: the comprehensive analysis of the converter, the alternative coupled inductor structures with the good performance, the current sensing of converter and the light-load efficiency improvement. They are investigated in this dissertation. The comprehensive analysis of the multiphase coupled-inductor buck converter is investigated. The n-phase (n>2) coupled-inductor buck converter with the duty cycle D>1/n hasn't been analyzed before. In this dissertation, the multiphase coupled-inductor buck converter is systematically analyzed for any phase number and any duty cycle condition. The asymmetric multiphase coupled-inductor buck converter is also analyzed. The existing coupled-inductor has a long winding path issue. In low-voltage, high-current applications, the short winding path is preferred because the winding loss dominates the inductor total loss and a short winding path can greatly reduce the winding loss. To solve this long winding path issue, several twisted-core coupled-inductors are proposed. The twisted-core coupled-inductor has such a severe 3D fringing effect that the conventional reluctance modeling method gives a poor result, unacceptable from the design point of view. By applying and extending Sullivan's space cutting method to the twisted core coupled inductor, a precise reluctance model of the twisted-core coupled-inductor is proposed. The reluctance model gives designers the intuition of the twisted-core coupled-inductors and facilitates the design of the twisted-core coupled-inductors. The design using this reluctance model shows good correlation between the design requirement and the design result. The developed space cutting method can also be used in other complex magnetic structures with the strong fringing effect. Today, more and more POL converters are integrated and the bottleneck of the integrated POL converters is the large inductor size. Different coupled-inductor structures are proposed to reduce the large inductor size and to improve the power density of the integrated POL converter. The investigation is based on the low temperature co-fire ceramic (LTCC) process. It is found that the side-by-side-winding coupled-inductor structure achieves a smaller footprint and size. With the two-segment B-H curve approximation, the proposed coupled-inductor structure can be easily modeled and designed. The designed coupled-inductor prototype reduces the magnetic size by half. Accordingly, the LTCC integrated coupled-inductor POL converter doubles the power density compared to its non-coupled-inductor POL counterpart and an amazing 500W/in³ power density is achieved. In a multiphase coupled-inductor converter, there are several coupled-inductor setups. For example, for a six-phase coupled-inductor converter, three two-phase coupled inductors, two three-phase coupled-inductors and one six-phase coupled inductors can be used. Different coupled-inductor setups are investigated and it is found that there is a diminishing return effect for both the steady-state efficiency improvement and the transient performance improvement when the coupling phase number increases. The conventional DCR current sensing method is a very popular current sensing method for today's multiphase non-coupled-inductor buck converters. Unfortunately, this current sensing method doesn't work for the multiphase coupled-inductor buck converter. To solve this issue, two novel DCR current sensing methods are proposed for the multiphase coupled-inductor buck converter. Although the multiphase coupled-inductor buck converters have shown a lot of benefits, they have a low efficiency under light-load working in DCM. Since the DCM operation of the multiphase coupled-inductor buck converter has never been investigated, they are analyzed in detail and the reason for the low efficiency is identified. It is found that there are more-than-one DCM modes for the multiphase coupled-inductor buck converter: DCM1, DCM2 …, and DCMn. In the DCM2, DCM3 …, and DCMn modes, the phase-currents reach zero-current more-than-once during one switching period, which causes the low efficiency of the multiphase coupledinductor buck converter in the light load. With the understanding of the low efficiency issue, the burst-in-DCM1-mode control method is proposed to improve the light load efficiency of the multiphase coupled-inductor buck converter. Experimental results prove the proposed solution. / Ph. D.

The suitable frequency range of electromagnetic interference (EMI) filters is always limited by the parasitic inductances and capacitances of components. The main object in this research is to develop design rules for lowering parasitic effects due to parasitic inductance of capacitor by using three coupled inductors. In this thesis, the properties and equivalent circuit of three coupled inductors are discussed first. It is found that two negative series inductances can be simultaneously obtained at two ports when the parameters of three coupled inductors are appropriately selected. These two negative inductances can be used to lower parasitic effect of capacitors. In other words, the EMI filter performance can be effectively improved by using this technology. Furthermore, method to completely reduce parasitic inductances is derived. The common mode insertion loss of this design is able to achieve at the rate of -60 dB/decade at high-frequency. For differential mode the insertion loss is even higher to the rate of -100 dB/decade.

In research environments, many soft switching inverters have been conceived, simulated, designed, implemented and proven to have advantages over hard switched inverters. To date however, no soft-switching inverters have reached commercial production for various reasons. The fixed timing coupled inductor soft-switching inverter is of interest because in simulation and previous implementation it exhibits load and source adaptability using simple RC timer circuitry and can be implemented with low cost active auxiliary devices. During the course of this implementation, it is noted that attempting to use excessively small/inexpensive active auxiliary devices has reliability ramifications related to device packaging. The issue of auxiliary active device reliability is conjectured upon by referencing available datasheet information, application specific requirements, device pulse testing and secondary research findings related to semiconductor failure characteristics. It is also noted that aspects of the simple fixed timing circuitry operation, in conjunction with coupled inductor and saturable inductor design, can lead to coupled inductor saturation if not properly addressed. Simulation is performed and validates various causes for this non-ideal behavior. / Master of Science

A multilevel Space Vector PWM (SVPWM) technique is developed for a 3-level 3-phase PWM Voltage Source Inverter using a 3-phase coupled inductor to ensure high performance operation. The selection of a suitable PWM switching scheme for the Coupled Inductor Inverter (CII) topology should be based on the dual requirements for a high-quality multilevel PWM output voltage together with the need to minimize high frequency currents and associated losses in the coupled inductor and the inverter switches. Compared to carrier-based multilevel PWM schemes, the space vector techniques provide a wider variety of choices of the available switching states and sequences. The precise identification of pulse placements in the SVPWM method is used to improve the CII performance. The successful operation of the CII topology over the full modulation range relies on selecting switching states where the coupled inductor presents a low winding current ripple and a high effective inductance between the upper and lower switches in each inverter leg. In addition to these requirements, the CII operation is affected by the imbalance inductor common mode dc current. When used efficiently, SVPWM allows for an appropriate balance between the need to properly manage the inductor winding currents and to achieve harmonic performance gains. A number of SVPWM strategies are developed, and suitable switching states are selected for these methods. Employing the interleaved PWM technique by using overlapping switching states, the interleaved Discontinuous SVPWM (DSVPWM) method, compared to other proposed SVPWM methods, doubles the effective switching frequency of the inverter outputs and, as a result, offers superior performance for the CII topology by reducing the inductor losses and switching losses. The inverter operation is examined by means of simulation and experimental testing. The experimental performance comparison is obtained for different PWM switching patterns. The inverter performance is affected by high-frequency inductor current ripple; the excessive inductor losses are reduced by the DSVPWM method. Additional experimental test results are carried out to obtain the inverter performance as a variable frequency drive when operated in steady-state and during transient conditions. The CII topology is shown to have great potential for variable speed drives. / Power Engineering and Power Electronics

Magnetic components, such as inductors and transformers, have important effects on the efficiency and performance of switching power supplies; their parasitic properties directly impact the high frequency properties which can cause lot-to-lot variation or unanticipated and non-ideal operation. They are also amongst the most problematic components to design, often requiring numerous design-prototype-test interactions. The electrostatic and electromagnetic analysis of wound components has become more important recently to predict their performance and frequency behavior. Accurate prediction and design of winding parasitic parameters of leakage inductance and winding capacitance for high frequency inductors and transformers in switching power supplies is fundamental to improve performance, lower cost, and speed time to market. This thesis presents a methodology and process to obtain accurate prediction of the inter- and intra-winding capacitances of high frequency magnetic components. Application examples considered are a single-winding choke, a coupled inductor filter, and a multi-winding transformer. Analytical approach for determination of parasitic capacitances in high frequency magnetic components will be covered also. Comparison of the FEA results using JMAG with experimental and empirical formula results show good agreement, supporting the method as a model-based design tool with the potential to significantly reduce the design-prototype-test cycle commonly needed with sophisticated magnetic designs.

The study involves the following stages: First, coupled-inductor and integrated magnetic structure used in Cuk converter circuit topologies are analyzed and the necessary information about these elements in circuit design is gathered. Also, benefits of using these magnetic elements are presented. Secondly / steady-state model, dynamic model and transfer functions of coupled-inductor Cuk converter topology are obtained via state-space averaging method. Third stage deals with determining the design criteria to be fulfilled by the implemented circuit. The selection of the circuit components and the design of the coupled-inductor providing ripple-free input current waveform are performed at this stage. Fourth stage introduces the experimental results of the implemented circuit operating in open loop mode. Besides, the controller design is carried out and the closed loop performance of the implemented circuit is presented in this stage.

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Lighting consumes approximately 20-25% of the energy produced worldwide. LED based lighting is rapidly becoming the preferred choice over incandescent and fluorescent based lighting. LEDs have advantages such as high efficacy, long operating lifetime and excellent lumen maintenance. Therefore, to gain benefits from LEDs for lighting purposes, they must be driven with efficient drivers which maintain high LED efficacy and long LED lifetime. A review of existing LED drivers is done, and their advantages and drawbacks are identified. Existing fault-tolerant drivers are also reviewed. Several dimming methods and their effects on the LED efficacy and lifetime are investigated. As a result, a converter with coupled inductors, suitable as an LED driver which has high efficiency and can maintain high LED efficacy, incorporated with a high efficiency dimming method, is chosen. For the proposed LED driver, a comprehensive analysis on the effects of coupling type and coupling coefficient on converter performance is done. This is carried out to establish the best coupled inductor structure and coupling coefficient, for the proposed LED driver. The coupled inductor obtained is used to achieve high LED efficacy and also used to eliminate the need for an output filtering capacitor. This results in a highly compact, high efficiency and low cost LED driver. A lossless method of LED string current sensing is proposed, so that driver efficiency is not negatively impacted. The LED driver and a digital control system are designed, with the fault-tolerant feature incorporated. The LED driver and the control system are simulated and practically implemented. The results obtained show excellent LED driver performance. The fault-tolerant feature can enable the driver to operate under fault conditions, saving repair costs and down time. Additionally, a novel digitally controlled LED driver, which can drive several independent multiple LED loads, is proposed. This novel driver is simulated and practically implemented; with the results showing excellent driver performance. The novel LED driver can simplify and reduce costs of existing LED lighting systems. / Dissertation (MEng)--University of Pretoria, 2013. / gm2014 / Electrical, Electronic and Computer Engineering / Unrestricted

As a scalable, high-efficiency, and simple converter topology, an interleaved, multiphase buck converter has been widely used to power microprocessors in information industry. As modern microprocessors continuously advance, the required current for high-performance microprocessors used in data center applications could be several hundreds of amperes with a current slew rate larger than 1000 A/μs. This poses great challenges for a high-efficiency, high-power-density voltage regulator design with a fast transient response. On the other hand, the design challenges of voltage regulators in mobile applications are also increasing due to the stringent requirement on the device thickness and the battery life. In a multiphase buck converter, discrete inductors are widely used as energy storage elements. However, this solution has a limited transient response with a large size of magnetic components. To overcome these issues, coupled inductor is proposed to realize a small steady-state current ripple, a fast transient response, and a small inductor size at the same time. Although lots of studies have been conducted in the topic of the coupled inductor, there are still several challenges unsolved in this area. These challenges are addressed through a comprehensive study in this dissertation. First, a comprehensive analysis of different coupled inductor structures is crucial to identify the benefits and limitations of each inductor structure and provide design guidance under different application requirements. Based on the coupling mechanism, different coupled inductor structures are categorized as a direct-coupled inductor (DCL), an indirect-coupled inductor (ICL) or a hybrid-coupled inductor (HCL) in this work. The performance of these three types of coupled inductors is analyzed in detail through the equivalent inductance analysis and the magnetic flux analysis. For the applications that require a small phase number, a DCL can achieve the smallest inductor size with a given inductance requirement. As the phase number increases, it is beneficial to use an ICL and an HCL due to their symmetrical, simple, and scalable inductor structures. As compared to an ICL, an HCL can achieve a smaller inductor size due to the flux-cancellation effect. The difference between a DCL, an ICL and an HCL are revealed quantitively with several design examples through this study. Second, the steady-state inductance (Lss) and the transient inductance (Ltr) are two key design parameters for coupled inductors. A large Lss and a small Ltr are preferred from the circuit performance point of view. However, there is a design conflict in an ICL and an HCL under the inductor size constraint, where reducing Ltr also results in a smaller Lss. A variable coupling coefficient concept is proposed to overcome this issue. With the same Lss, the proposed method can achieve a smaller Ltr during load transients as compared with the conventional method. This concept is realized by applying a nonlinear inductor in the additional winding loop with the current in this loop as the control source. Compared with the conventional structure, the proposed structure can achieve a great output voltage spike reduction and output capacitance reduction. Third, although an ICL and an HCL are promising candidates for multiphase coupled inductors, an extra inductor is required in the additional winding loop to adjust the coupling coefficient. This additional inductor occupies extra space. To shrink the total inductor size, several improved magnetic core structures are proposed to achieve the controllable coupling through the magnetic integration for an ICL and an HCL. Furthermore, the thickness of the core plate can be significantly reduced by the improved core structure for an HCL. Overall, it is demonstrated that the inductor footprint is greatly reduced by the proposed core structure, as compared with the conventional solution. Lastly, a novel PCB-embedded coupled inductor structure is proposed for a 20MHz integrated voltage regulator (IVR) for mobile applications. To achieve a small inductor footprint and a low profile, the inductor structure with a lateral flux pattern and direct coupling is adopted. Compared with the state-of-the-art solution, the proposed structure can adjust the coupling in a simple core structure by changing the inductor winding pattern. The proposed structure integrates multiple inductors into one magnetic core and is embedded into PCB with a total thickness of 0.54 mm. In contrast to prior arts, the proposed inductor structure features a large inductance density and quality factor with a much smaller DC resistance (DCR), thus is seen as a promising candidate for IVR applications. / Doctor of Philosophy / As modern microprocessors continuously advance in the information industry, the required current for high-performance microprocessors used in data center applications could be several hundreds of amperes with a current slew rate larger than 1000 A/μs. This poses great challenges for the power converter design. On the other hand, the design challenges of power converters in mobile applications are also increasing due to the stringent requirement on the device thickness and the battery life. As a scalable, high-efficiency, and simple converter topology, an interleaved, multiphase buck converter has been widely used to power these processors. In a multiphase buck converter, discrete inductors are widely used as energy storage elements. However, this solution has a limited transient response with a large size of magnetic components. To overcome these issues, coupled inductor is proposed to realize a small steady-state current ripple, a fast transient response, and a small inductor size at the same time. Although lots of studies have been conducted in the topic of the coupled inductor, there are still several challenges unsolved in this area. These challenges are addressed through a comprehensive study in this dissertation. First, a comprehensive analysis and comparison of different coupled inductor structures is crucial to identify the benefits and limitations of each inductor structure and provide design guidance under different application requirements. Based on the coupling mechanism, different coupled inductor structures are categorized as a direct-coupled inductor (DCL), an indirect-coupled inductor (ICL) or a hybrid-coupled inductor (HCL) in this work. The performance of these three types of coupled inductors is analyzed in detail through the equivalent inductance analysis and the magnetic flux analysis. The difference between a DCL, an ICL and an HCL are revealed quantitively with several design examples through this study. Second, the steady-state inductance (Lss) and the transient inductance (Ltr) are two key design parameters for coupled inductors. A large Lss and a small Ltr are preferred from the circuit performance point of view. However, there is a design conflict in an ICL and an HCL under the inductor size constraint, where reducing Ltr also results in a smaller Lss. A variable coupling coefficient concept is proposed to overcome this issue. This concept is realized by applying a nonlinear inductor in the conventional structure. Compared with the conventional structure, the proposed structure can achieve a great output voltage spike reduction and output capacitance reduction. Third, although an ICL and an HCL are promising candidates for multiphase coupled inductors, an extra inductor is required in the additional winding loop to adjust the coupling coefficient. This additional inductor occupies extra space. To shrink the total inductor size, several improved magnetic core structures are proposed to achieve the controllable coupling through the magnetic integration for an ICL and an HCL. Lastly, a novel PCB-embedded coupled inductor structure is proposed for a 20MHz integrated voltage regulator (IVR) for mobile applications. Compared with the state-of-the-art solution, the proposed structure can adjust the coupling in a simple core structure by changing the inductor winding pattern. In contrast to prior arts, the proposed inductor structure features a large inductance density and quality factor with a much smaller DC resistance (DCR), thus is seen as a promising candidate for IVR applications.

The data center serves as the hardware foundation for artificial intelligence (AI) and cloud computing, constituting a global market that has surpassed $200 billion and is experiencing rapid growth. It is estimated that data centers contribute to 1.7-2.2% of the world's electricity generation. Conversely, up to 80% of the long-term operational expenditure of data centers is allocated to electricity consumption. Consequently, enhancing the efficiency of electric energy conversion in data centers is not only economically advantageous but also crucial for achieving carbon-neutral objectives. Through collaborative efforts between the industrial and academic sectors, substantial advancements have been achieved in the energy conversion efficiency of data centers. Most converters within the data center power architecture now boast efficiencies exceeding 99%. However, the bottleneck for further improvements in system efficiency lies in the voltage regulator modules (VRMs), which grapple with challenges such as high conversion ratios, elevated output currents, and substantial load transients. These challenges are particularly pronounced for AI processors and graphics processing units (GPUs), given their heightened power demands compared to conventional central processing units (CPUs). To enhance system efficiency, a revolutionary shift in power architecture has been introduced, advocating for the adoption of a 48 V data center power architecture to replace the conventional 12 V architecture. The higher 48 V bus voltage significantly reduces distribution loss on the bus. However, the primary challenge lies in managing high step-down voltage conversion while maintaining high efficiency. Additionally, high-performance microprocessors, including CPUs, GPUs, application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs), require hundreds of amperes of current at low voltage levels (e.g., GPUs need >220 A at <1.85 V, CPUs need >1000 A at <1.0 V). An unavoidable consequence of upscaling processor current and size is the substantial resistive loss in VRMs. This is because such loss scales with the square of the current [I2R], and the power path area (and resistance R) expands with the processor size. The Power Delivery Network (PDN) resistance in the "last inch" of the power delivery path is becoming a limiting factor in processor performance and system efficiency. The key to reducing the I2R loss is minimizing the distance between the VRMs and processors by utilizing ultra-high power density VRMs. Furthermore, the design of Voltage Regulator Modules (VRMs) for high-performance microprocessors encounters additional formidable challenges, especially when dealing with the requirements of contemporary computing architectures. The key hurdles encompass achieving high efficiency, handling low output voltage, accommodating wide voltage ranges, managing elevated output currents, and addressing significant load transients. These challenges prompt both academia and industry to explore novel topologies, innovative magnetic integration methods, and advanced control strategies. The prevailing trend in state-of-the-art 48V solutions centers around the adoption of two-stage configurations, wherein the second stage can leverage conventional 12V solutions. However, this approach imposes limitations on power density and efficiency, given that power traverses two cascaded DC/DC converters. Additionally, the footprint of decoupling capacitors and I2R loss on the intermedia bus between the two stages is emerging as a noteworthy consideration in designs. In response to these challenges, a novel proposition introduces a single-stage 48V coupled-transformer voltage regulator (CTVR) tailored for high-performance microprocessors. This innovative design aims to deliver ultra-high power density and superior efficiency. The converter employs a unique magnetic structure that integrates transformers and coupled inductors from multiple current-doubler rectifiers. Significantly, by utilizing the magnetizing inductors of transformers as output inductors, there is a substantial reduction in the size of magnetic components. Various implementations are explored, each addressing specific design objectives. Initially, a single-stage coupled-transformer voltage regulator (CTVR) with discrete magnetics is presented, offering a 48V solution while maintaining a comparable size and cost to a state-of-the-art 12V multiphase buck regulator. Leveraging the indirect-coupling concept, magnetic components are standardized, enabling scalability and facilitating multiphase operation. A prototype is constructed and tested to validate the CTVR's performance. With a 48V input and 1.8V output, the peak efficiency registers at 92.1%, and the power area density is 0.45 W/mm2. However, voltage ringing is observed in both primary and secondary switches due to a larger leakage inductance and hard-switching operation. Subsequently, a transition to soft-switching operation is implemented to address the voltage ringing issue. The leakage inductance is intentionally designed to supply energy for zero-voltage switching (ZVS) of primary switches, turning the previously perceived drawback into an opportunity for efficiency improvement. As a result, testing demonstrates a peak efficiency increase of more than 1%, reaching 93.6%. Furthermore, efforts are made to enhance small leakage inductance by employing well-interleaved printed circuit board (PCB) windings. Following a series of design optimizations, the prototype achieves a peak efficiency of 93.1% and a remarkable power density of 1037 W/in3, accounting for gate driver loss and size. Despite an increase in cost associated with PCB windings, this proposed solution attains the highest power density and stands as the pioneering 48V single-stage design surpassing 1000 W/in3 power density. When prioritizing efficiency in the design, the quasi-parallel Sigma converter emerges as another optimal choices for a 48V solution. However, the intricate and distinctive quasi-parallel structure of the Sigma converter necessitates a thorough examination of its control mechanism, particularly in light of the rapid load transient response requirements. To address this, an adaptive voltage positioning (AVP) design for the Sigma converter is introduced, employing enhanced V2 control. Guidelines and limitations are provided to stabilize the converter and enhance its overall performance. Ultimately, the AVP function and load transient performance are substantiated through simulation and experimental results. / Doctor of Philosophy / Data center is the hardware foundation of artificial intelligence (AI) and cloud computing. The global data center market has exceeded $200 billion and is fast growing. It is estimated that data center accounts for 1.7~2.2% of the world's electricity generation. On the other hand, up to 80% of the long-term operation expenditure of data centers is electricity. Thus, improving the efficiency of electric energy conversion in data centers is economically beneficial and critical to reaching the carbon neutral goal. The bottleneck for further improvements in system efficiency lies in the voltage regulator modules (VRMs), which grapple with challenges such as high conversion ratios, elevated output currents, and substantial load transients. These challenges are particularly pronounced for AI processors and graphics processing units (GPUs). In response to these challenges, a novel proposition introduces a single-stage 48V coupled-transformer voltage regulator (CTVR) tailored for high-performance microprocessors. This innovative design aims to deliver ultra-high power density and superior efficiency. The converter employs a unique magnetic structure that integrates transformers and coupled inductors from multiple current-doubler rectifiers. Significantly, by utilizing the magnetizing inductors of transformers as output inductors, there is a substantial reduction in the size of magnetic components. Various implementations are explored, each addressing specific design objectives. When prioritizing efficiency in the design, the quasi-parallel Sigma converter emerges as another optimal choices for a 48V solution. However, the intricate and distinctive quasi-parallel structure of the Sigma converter necessitates a thorough examination of its control mechanism, particularly in light of the rapid load transient response requirements. To address this, an adaptive voltage positioning (AVP) design for the Sigma converter is introduced, employing enhanced V2 control. Guidelines and limitations are provided to stabilize the converter and enhance its overall performance. Ultimately, the AVP function and load transient performance are substantiated through simulation and experimental results.