The first topic of this thesis is to propose a novel voltage-to-frequency converter (VFC) to provide high sensitivity. The VFC circuit is composed of one current mirror, one current multiplier, and voltage window comparators. The proposed VFC tracks the variations of the stored charge of a built-in capacitor. The voltage window comparator monitors the voltage of the capacitor to determine whether the output is pulled high or pulled down. The worth-case linear range of the output frequency of the proposed VFC is 0 to 55 MHz provided that the input voltage is 0 to 0.9 V. The error is less than 9% while the power dissipation is 0.218 mW. The second topic is to carry out a novel CMOS current-mode high- speed sense amplifier (SA). The proposed SA is composed by cascading a current-mode sense amplifier and a voltage-mode sense amplifier. The small input impedance of the current-mode amplifier alleviates the loading effect on the bitlines of SRAM cells such that the sensing speed is enhanced. The voltage-mode amplifier is responsible for boosting the logic levels to full swing. The worst access time of the proposed design is found to be less than 1.26 ns with a 1 pF load on outputs. The power dissipation is merely 0.835 mW at 793 MHz.

In this thesis, the possibility of applying digital current mode control on multiple-input (MI) converters is studied. As for MI topologies having a central energy transfer inductor, the predictive constant on-time current-mode control can greatly reduce both the design and digital realization efforts needed. By doing digital constant on-time current-mode control, the control of MI buck and MI buck-boost converters can be simplified into an equivalent-single-input converter control problem. The small signal models of digital constant on-time controlled single-input (SI), MI buck and SI, MI buck-boost converters in both CCM and DCM are proposed. Simulations and experiments were built to verify the proposed models. / text

Ultra-low-power circuits are becoming more desirable due to growing portable device markets and they are also becoming more interesting and applicable today in biomedical, pharmacy and sensor networking applications because of the nano-metric scaling and CMOS reliability improvements. In this thesis, three main achievements are presented in ultra-low-power adders. First, a new majority function algorithm for carry and the sum generation is presented. Then with this algorithm and implied new architecture, we achieved a circuit with 75mV supply voltage operation. Last but not least, a 64 bit current-mode majority-function adder based on the new architecture and algorithm is successfully tested at 75mV supply voltage. The circuit consumed 4.5nW or 3.8pJ in one of the worst conditions.

abstract: Current sensing ability is one of the most desirable features of contemporary current or voltage mode controlled DC-DC converters. Current sensing can be used for over load protection, multi-stage converter load balancing, current-mode control, multi-phase converter current-sharing, load independent control, power efficiency improvement etc. There are handful existing approaches for current sensing such as external resistor sensing, triode mode current mirroring, observer sensing, Hall-Effect sensors, transformers, DC Resistance (DCR) sensing, Gm-C filter sensing etc. However, each method has one or more issues that prevent them from being successfully applied in DC-DC converter, e.g. low accuracy, discontinuous sensing nature, high sensitivity to switching noise, high cost, requirement of known external power filter components, bulky size, etc. In this dissertation, an offset-independent inductor Built-In Self Test (BIST) architecture is proposed which is able to measure the inductor inductance and DCR. The measured DCR enables the proposed continuous, lossless, average current sensing scheme. A digital Voltage Mode Control (VMC) DC-DC buck converter with the inductor BIST and current sensing architecture is designed, fabricated, and experimentally tested. The average measurement errors for inductance, DCR and current sensing are 2.1%, 3.6%, and 1.5% respectively. For the 3.5mm by 3.5mm die area, inductor BIST and current sensing circuits including related pins only consume 5.2% of the die area. BIST mode draws 40mA current for a maximum time period of 200us upon start-up and the continuous current sensing consumes about 400uA quiescent current. This buck converter utilizes an adaptive compensator. It could update compensator internally so that the overall system has a proper loop response for large range inductance and load current. Next, a digital Average Current Mode Control (ACMC) DC-DC buck converter with the proposed average current sensing circuits is designed and tested. To reduce chip area and power consumption, a 9 bits hybrid Digital Pulse Width Modulator (DPWM) which uses a Mixed-mode DLL (MDLL) is also proposed. The DC-DC converter has a maximum of 12V input, 1-11 V output range, and a maximum of 3W output power. The maximum error of one least significant bit (LSB) delay of the proposed DPWM is less than 1%. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011

学位授与大学：京都大学 ; 取得学位: 博士(工学) ; 学位授与年月日: 2007-09-25 ; 学位の種類: 新制・課程博士 ; 学位記番号: 工博第2864号 ; 請求記号: 新制/工/1421 ; 整理番号: 25549 / Kyoto University (京都大学) / 0048 / 新制・課程博士 / 博士(工学) / 甲第13393号 / 工博第2864号 / 新制||工||1421(附属図書館) / 25549 / UT51-2007-Q794 / 京都大学大学院工学研究科電気工学専攻 / (主査)教授 引原 隆士, 教授 小林 哲生, 准教授 中村 武恒 / 学位規則第4条第1項該当

abstract: With the push for integration, a slew of modern switching power management circuits are operating at higher switching frequencies in order to reduce passive filter sizes. But while these switching regulators provide power conversion at high efficiencies, their output is prone to ripples due to the inherent switching behavior. These switching regulators use linear-low dropout regulators (LDOs) downstream to provide clean supplies. Typically, these LDOs have good power supply rejection (PSR) at lower frequencies but this degrades at higher frequencies. Therefore, some residual ripple is still manifested on the output. Because of this, high power supply rejection (PSR) with a wide rejection frequency band is becoming a critical requirement in linear low-dropout regulators (LDOs) used in complex systems- on-chip (SOCs). Typical LDOs achieve higher PSR within their loop-bandwidth; however, their supply rejection performance degrades with reduced loop-gain outside their loop- bandwidth. The LDOs with external filtering capacitors may also have spectral peaking in their PSR response, causing excess system- level supply noise. This work presents an LDO design approach, which achieves a PSR of higher than 68 dB up to 2 MHz frequency and over a wide range of loads up to 250 mA. The wide PSR bandwidth is achieved using a current-mode feedforward ripple canceller (CFFRC) amplifier which provides up to 25 dB of PSR improvement. The feedforward path gain is inherently matched to the forward gain of the LDO, not requiring calibration. The LDO has a fast load transient response with a recovery time of 6.1μs and has a quiescent current of 5.6μA. For a full load transition, the LDO achieves settling with overshoot and undershoot voltages below 27.6 mV and 36.36 mV, respectively. The LDO is designed and fabricated in a 180 nm bipolar/CMOS/DMOS (BCD) technology. The CFFRC amplifier helps to achieve low quiescent power due to its inherent current mode nature, eliminating the need for supply ripple summing amplifiers and adaptive biasing. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2020

Master´s thesis deals about design of symmetrical converters voltage on current and current on voltage. These converters will be used for measuring frequency characteristics of differential frequency filters. Current feedback amplifier was used as active element. Some circuits useful for this function were chosen. Various integrated circuits were put into these circuits. All variations were simulated in computer program Orcad. In terms of computer simulations the best variation was chosen. Selected variants were practically verified and control measuring were realized.

The master thesis focuses on design of fully-differential frequency filters with modern active components in current mode. First part informs about problems concerning analogue frequency filters and creating differential structures. Second part deals with methods of create filters and used active components - DACA (Digital Adjustable Current Amplifier) and MO-CF (Multiple Output Current Follower). Own design of differential filters is divided on two parts. In the first part of design results there are filters created with synthetic higher-order elements. There are presented circuit structures implementing the third order low pass filter and high pass filter. In the second part are designed filters with signal flow graphs. The first circuit implementing low pass, high pass, band pass, band rejection and all-pass filter. The second circuit is with help of the same set of current amplification by DACA components tuning of the natural frequency. For this circuit was make sensitivity analysis. In the final part is practical implementation of the differential frequency filter for tuning of the natural frequency and summarises the thesis.

This master´s thesis deals with the differential filters working in the current mode. It is dealt with the design methodologies of these filters and conversion circuits from voltage to current mode. Own work deals with 4 types of differential participation of structures. In this work there has been used programs SNAP and OrCAD. These programs were used for simulations of filters to proposed proper design. Results from this thesis is showed by graphs.

The diploma thesis is describing how forward converter works. The diploma thesis presents the function of forward converter with demagnetizing winding and presents the function of two-switched forward converter. The diploma thesis descibes the behaviour of continuous current mode and discontinuous current mode. The diploma thesis explains the reasons for implementation feedback and presents the basic types of compensations. The project deals with AC analysis of two-switched forward converter with continuous peak current mode control. The Analog prototyping metod is used for digital control design. The function of the converter was tested in laboratory. The laboratory results have been compared with the theoretical and the simulation results.