As a very special DC-DC converter, VRM (Voltage Regulator Module) design must follow the fast-developing trend of microprocessors. The design challenges are the high current, high di/dt, and stringent load-line requirement. When the energy is transferred from the input of a VRM, through the VRM, then through the power delivery path to the processor, it needs sufficient capacitors to relay this energy. The capacitors' number appears to be unrealistically large if we follow today's approach for the future processors. High frequency VRM with high control bandwidth can solve this problem, however, the degradation of efficiency makes the conventional buck converter and the hard-switching isolated topologies incapable of operating at higher frequency. The research goal is to develop novel means that can help a high-output- current VRM run efficiently at high frequency. A novel Complementary Controlled Bridge (CCB) self-driven concept is proposed. With the proposed self-driven scheme, the combination of the ZVS technique and the self-driven technique recycles the gate driving energy by making use of the input capacitor of the secondary- side synchronous rectifier (SR) as the snubber capacitor of the primary-side switches. Compared to the external driver, the proposed converter can save driving loss and synchronous rectifier body diode conduction loss. Additionally, compared to the existing level-shifted self-driven scheme for bridge-type symmetrical topologies, its gate signal ringing is small and suitable for high-frequency applications. Although the CCB self-driven VRM reduces the switching frequency-related losses significantly, the conduction loss is still high. Inspired by the current-doubler concept, a novel ZVS current-tripler DC-DC converter is proposed in this work. By utilizing more SR devices to share the current during the freewheeling period, the SR conduction loss is reduced. The current-tripler DC-DC converter has a delta/delta connected transformer that can be implemented with integrated magnetics. The transformer then becomes an integrated magnetic with distributed windings, which is preferred in high current applications. The current-tripler DC-DC converter in fact meets the requirements for the CCB self-driven scheme. The two concepts are then combined with an integrated gate drive transformer. The proposed CCB self-driven concept and current-tripler concept can both be applied to the 12V non-isolated VRMs. The proposed topology is basically a buck-derived soft-switching topology with duty cycle extension and SR device self-driven capabilities. Because there is no isolation requirement, the SR gate driving becomes so simple that the voltage at the complementary controlled bridge can be used to directly drive the SR gate. Both the gate driving loss and the SR body diode conduction loss are reduced. The proposed circuit achieves similar overall efficiency to a conventional 300kHz buck converter running at 1MHz. All the circuits proposed in this dissertation can use coupling inductors to improve both the steady-state efficiency and dynamic performances. The essence of the coupling inductors concept is to provide different equivalent inductances for the steady state and the transient. Moreover, when a current loop becomes necessary to achieve proper current sharing among phases, the current loop sample hold effect will make it difficult to push the bandwidth. The sample hold effect is alleviated by the coupling inductors concept. A small-signal model is proposed to study the system dynamic performance difference with different coupling inductor designs. As the verification, the coupling concept is applied to the 12V non-isolated CCB self-driven VRM and the bandwidth as high as one third of the switching frequency is achieved, which means a significant output capacitor reduction. / Ph. D.

With the rapid development of microprocessor and semiconductor technology, industry continues to update the requirements for power supplies. For telecommunication and computing system applications, power supplies require increasing current level while the supply voltage keeps decreasing. For example, the Intel's CPU core voltage decreased from 2 volt in 1999 to 1 volt in 2005 while the supply current increased from 20A in 1999 to up to 100A in 2005. As a result, low-voltage high-current high efficiency dc-dc converters with high power-density are demanded for state-of-the-art applications and also the future applications. Half-bridge dc-dc converter with current-doubler rectification is regarded as a good topology that is suitable for high-current low-voltage applications. There are three control schemes for half-bridge dc-dc converters and in order to provide a valid unified analog model for optimal compensator design, the analog state-space modeling and small signal modeling are studied in the dissertation and unified state-space and analog small signal model are derived. In addition, the digital control gains a lot of attentions due to its flexibility and re-programmability. In this dissertation, a unified digital small signal model for half-bridge dc-dc converter with current doubler rectifier is also developed and the digital compensator based on the derived model is implemented and verified by the experiments with the TI DSP chip. In addition, although current doubler rectifier is widely used in industry, the key issue is the current sharing between two inductors. The current imbalance is well studied and solved in non-isolated multi-phase buck converters, yet few discusse this issue in the current doubler rectification topology within academia and industry. This dissertation analyze the current sharing issue in comparison with multi-phase buck and one modified current doubler rectifier topology is proposed to achieve passive current sharing. The performance is evaluated with half bridge dc-dc converter; good current sharing is achieved without additional circuitry. Due to increasing demands for high-efficiency high-power-density low-voltage high current topologies for future applications, the thermal management is challenging. Since the secondary-side conduction loss dominates the overall power loss in low-voltage high-current isolated dc-dc converters, a novel current tripler rectification topology is proposed. Theoretical analysis, comparison and experimental results verify that the proposed rectification technique has good thermal management and well-distributed power dissipation, simplified magnetic design and low copper loss for inductors and transformer. That is due to the fact that the load current is better distributed in three inductors and the rms current in transformer windings is reduced. Another challenge in telecommunication and computing applications is fast transient response of the converter to the increasing slew-rate of load current change. For instance, from Intel's roadmap, it can be observed that the current slew rate of the age regulator has dramatically increased from 25A/uS in 1999 to 400A/us in 2005. One of the solutions to achieve fast transient response is secondary-side control technique to eliminate the delay of optocoupler to increase the system bandwidth. Active-clamp half bridge dc-dc converter with secondary-side control is presented and one industry standard 16th prototype is built and tested; good efficiency and transient response are shown in the experimental section. However, one key issue for implementation of secondary-side control is start-up. A new zero-voltage-switching buck-flyback isolated dc-dc converter with synchronous rectification is proposed, and it is only suitable for start-up circuit for secondary-side controlled converter, but also for house-keeping power supplies and standalone power supplies requiring multi-outputs.