11 
Aspects of ListofTwo DecodingEriksson, Jonas January 2006 (has links)
<p>We study the problem of list decoding with focus on the case when we have a list size limited to two. Under this restriction we derive general lower bounds on the maximum possible size of a listof2decodable code. We study the set of correctable error patterns in an attempt to obtain a characterization. For a special family of ReedSolomon codes  which we identify and name 'classI codes'  we give a weightbased characterization of the correctable error patterns under listof2 decoding. As a tool in this analysis we use the theoretical framework of Sudan's algorithm. The characterization is used in an exact calculation of the probability of transmission error in the symmetric channel when listof2 decoding is used. The results from the analysis and complementary simulations for QAMsystems show that a listof2 decoding gain of nearly 1 dB can be achieved.</p><p>Further we study Sudan's algorithm for list decoding of ReedSolomon codes for the special case of the classI codes. For these codes algorithms are suggested for both the first and second step of Sudan's algorithm. Hardware solutions for both steps based on the derived algorithms are presented.</p>

12 
Computations in Prime Fields using Gaussian IntegersEngström, Adam January 2006 (has links)
<p>In this thesis it is investigated if representing a field <i>Z</i><i>p</i><i>, p</i> = 1 (mod 4) prime, by another field <i>Z[i]</i>/ < <i>a + bi </i>> over the gaussian integers, with <i>p</i> = <i>a</i><i>2</i><i> + b</i><i>2</i>, results in arithmetic architectures using a smaller number of logic gates. Only bit parallell architectures are considered and the programs Espresso and SIS are used for boolean minimization of the architectures. When counting gates only NAND, NOR and inverters are used.</p><p>Two arithmetic operations are investigated, addition and multiplication. For addition the architecture over<i> Z[i]/ < a+bi ></i> uses a significantly greater number of gates compared with an architecture over<i> Z</i><i>p</i>. For multiplication the architecture using gaussian integers uses a few less gates than the architecture over <i>Z</i><i>p</i> for <i>p</i> = 5 and for<i> p</i> = 17 and only a few more gates when <i>p</i> = 13. Only the values 5, 13, 17 have been compared for multiplication. For addition 12 values, ranging from 5 to 525313, have been compared.</p><p>It is also shown that using a blif model as input architecture to SIS yields much better performance, compared to a truth table architecture, when minimizing.</p>

13 
Cardinality for optical orthogonal codes with variable length and weightIsaksson, Erica January 2006 (has links)
<p>To let many users beneﬁt from the high speed communication in an optical ﬁber, a way to share the channel is needed. One way to share the channel between the users is the multiple access technique of Code Division Multiple Access, CDMA. This technique is based on coding. By assigning the users diﬀerent codewords, the receiver is able to distinguish the information sent from each user. One family of codes suitable to use in a ﬁber optic network is the constant weight Optical Orthogonal Codes, OOC.</p><p>To inﬂuence the users interference tolerability it is possible to assign the users codewords of the same length but with diﬀerent weights. By letting the users have codewords of diﬀerent length it is possible to have diﬀerent data rates in the system. These two versions of optical orthogonal codes, with variable length and weight, are investigated in this thesis for their cardinality. The variable weight and variable length codes were created by combining optical orthogonal codes with diﬀerent parameters.</p><p>I have found that for variable length OOC:s of weight 2 it seems to be possible to increase the cardinality of a code, but for codes with higer weights than that, it is better that all users are assigned codewords of the same length. But since an upper bound for the cardinality of these types of codes has not been found, it is not possible to verify if this conclusion is correct. For variable weight OOC:s it is found that it is only possible to increase the cardinality of small, not optimal, codes. For codes including many codewords it is rarely possible to include more codewords without breaking the conditions on cross correlation between the codewords.</p>

14 
Hardware Accelerator for Duobinary CTC decoding : Algorithm Selection, HW/SW Partitioning and FPGA ImplementationBjärmark, Joakim, Strandberg, Marco January 2006 (has links)
<p>Wireless communication is always struggling with errors in the transmission. The digital data received from the radio channel is often erroneous due to thermal noise and fading. The error rate can be lowered by using higher transmission power or by using an effective error correcting code. Power consumption and limits for electromagnetic radiation are two of the main problems with handheld devices today and an efficient error correcting code will lower the transmission power and therefore also the power consumption of the device. </p><p>Duobinary CTC is an improvement of the innovative turbo codes presented in 1996 by Berrou and Glavieux and is in use in many of today's standards for radio communication i.e. IEEE 802.16 (WiMAX) and DVBRSC. This report describes the development of a duobinary CTC decoder and the different problems that were encountered during the process. These problems include different design issues and algorithm choices during the design.</p><p>An implementation in VHDL has been written for Alteras Stratix II S90 FPGA and a referencemodel has been made in Matlab. The model has been used to simulate bit error rates for different implementation alternatives and as bittrue reference for the hardware verification.</p><p>The final result is a duobinary CTC decoder compatible with Alteras Stratix II designs and a reference model that can be used when simulating the decoder alone or the whole signal processing chain. Some of the features of the hardware are that block sizes, puncture rates and number of iterations are dynamically configured between each block Before synthesis it is possible to choose how many decoders that will work in parallel and how many bits the soft input will be represented in. The circuit has been run in 100 MHz in the lab and that gives a throughput around 50Mbit with four decoders working in parallel. This report describes the implementation, including its development, background and future possibilities.</p>

15 
Positionering i GSMnätverkPersson, Patrik January 2007 (has links)
<p>Merparten av de kommersiella system för mobilkommunikation som finns och byggs i världen idag bygger fortfarande på GSM, antalet abbonnenter är över 2 miljarder. För att utöka funktionaliteten med mobila terminaler har det forskats på att införa positionering i GSMnätverk. Tjänster som använder abbonnentens positionsinformation kallas Location Based Service och de ger möjlighet att utöka funktionaliteten och spara användaren av tjänsten arbete. </p><p>Rapporten beskriver olika tekniker för positionering och slutsatsen att CGITA är den teknik som positioneringen ska byggas på. Denna teknik finns tillgänglig hos de svenska operatörerna idag och för att kommunicera med dem används Mobile Location Protocol 3.0.0. Implementation av positioneringen realiserades i en J2EEmiljö i form av en WebLogic Server 8.1 med hjälp av Enterprise Java Beans och Java Connector Architecture. Prototypen verifierades med hjälp av en emulator till Ericsson Mobile Positioning System som klarar av att hantera Mobile Location Protocol 3.0.0.</p>

16 
Aspects of ListofTwo DecodingEriksson, Jonas January 2006 (has links)
We study the problem of list decoding with focus on the case when we have a list size limited to two. Under this restriction we derive general lower bounds on the maximum possible size of a listof2decodable code. We study the set of correctable error patterns in an attempt to obtain a characterization. For a special family of ReedSolomon codes  which we identify and name 'classI codes'  we give a weightbased characterization of the correctable error patterns under listof2 decoding. As a tool in this analysis we use the theoretical framework of Sudan's algorithm. The characterization is used in an exact calculation of the probability of transmission error in the symmetric channel when listof2 decoding is used. The results from the analysis and complementary simulations for QAMsystems show that a listof2 decoding gain of nearly 1 dB can be achieved. Further we study Sudan's algorithm for list decoding of ReedSolomon codes for the special case of the classI codes. For these codes algorithms are suggested for both the first and second step of Sudan's algorithm. Hardware solutions for both steps based on the derived algorithms are presented.

17 
Architecture for a remote diagnosis system used in heavyduty vehiclesBjörkman, Anders January 2008 (has links)
The diagnosis system of a Scania vehicle is an indispensable tool for workshop personnel and engineers in their work. Today Scania has a system for fetching diagnostic information from field test vehicles remotely and store them in a database, so called remote diagnosis. This saves the engineers much time by not having to visit every vehicle. The system uses a Windows based onboard PC in the vehicle called an Interactor. The Interactor has a telematic unit for communication with Scanias Fleet Management System and the CANbus in the vehicle. In the next generation of the Interactor, its telematic unit is to be replaced by a Linux based telematic unit called the Communicator 200 (C200). The purpose of this master project is to create a new architecture for a remote diagnosis system that uses the new telematic unit Communicator 200. <br />The thesis gives an analysis of the current remote diagnosis system used at Scania and proposes an architecture for a new generation remote diagnosis system using the C200. Also a system for demonstrating how to perform remote diagnosis over the C200 has been built. The thesis describes the operation and how the demonstration system was implemented.

18 
Computations in Prime Fields using Gaussian IntegersEngström, Adam January 2006 (has links)
In this thesis it is investigated if representing a field Zp, p = 1 (mod 4) prime, by another field Z[i]/ < a + bi > over the gaussian integers, with p = a2 + b2, results in arithmetic architectures using a smaller number of logic gates. Only bit parallell architectures are considered and the programs Espresso and SIS are used for boolean minimization of the architectures. When counting gates only NAND, NOR and inverters are used. Two arithmetic operations are investigated, addition and multiplication. For addition the architecture over Z[i]/ < a+bi > uses a significantly greater number of gates compared with an architecture over Zp. For multiplication the architecture using gaussian integers uses a few less gates than the architecture over Zp for p = 5 and for p = 17 and only a few more gates when p = 13. Only the values 5, 13, 17 have been compared for multiplication. For addition 12 values, ranging from 5 to 525313, have been compared. It is also shown that using a blif model as input architecture to SIS yields much better performance, compared to a truth table architecture, when minimizing.

19 
Cardinality for optical orthogonal codes with variable length and weightIsaksson, Erica January 2006 (has links)
To let many users beneﬁt from the high speed communication in an optical ﬁber, a way to share the channel is needed. One way to share the channel between the users is the multiple access technique of Code Division Multiple Access, CDMA. This technique is based on coding. By assigning the users diﬀerent codewords, the receiver is able to distinguish the information sent from each user. One family of codes suitable to use in a ﬁber optic network is the constant weight Optical Orthogonal Codes, OOC. To inﬂuence the users interference tolerability it is possible to assign the users codewords of the same length but with diﬀerent weights. By letting the users have codewords of diﬀerent length it is possible to have diﬀerent data rates in the system. These two versions of optical orthogonal codes, with variable length and weight, are investigated in this thesis for their cardinality. The variable weight and variable length codes were created by combining optical orthogonal codes with diﬀerent parameters. I have found that for variable length OOC:s of weight 2 it seems to be possible to increase the cardinality of a code, but for codes with higer weights than that, it is better that all users are assigned codewords of the same length. But since an upper bound for the cardinality of these types of codes has not been found, it is not possible to verify if this conclusion is correct. For variable weight OOC:s it is found that it is only possible to increase the cardinality of small, not optimal, codes. For codes including many codewords it is rarely possible to include more codewords without breaking the conditions on cross correlation between the codewords.

20 
Hardware Accelerator for Duobinary CTC decoding : Algorithm Selection, HW/SW Partitioning and FPGA ImplementationBjärmark, Joakim, Strandberg, Marco January 2006 (has links)
Wireless communication is always struggling with errors in the transmission. The digital data received from the radio channel is often erroneous due to thermal noise and fading. The error rate can be lowered by using higher transmission power or by using an effective error correcting code. Power consumption and limits for electromagnetic radiation are two of the main problems with handheld devices today and an efficient error correcting code will lower the transmission power and therefore also the power consumption of the device. Duobinary CTC is an improvement of the innovative turbo codes presented in 1996 by Berrou and Glavieux and is in use in many of today's standards for radio communication i.e. IEEE 802.16 (WiMAX) and DVBRSC. This report describes the development of a duobinary CTC decoder and the different problems that were encountered during the process. These problems include different design issues and algorithm choices during the design. An implementation in VHDL has been written for Alteras Stratix II S90 FPGA and a referencemodel has been made in Matlab. The model has been used to simulate bit error rates for different implementation alternatives and as bittrue reference for the hardware verification. The final result is a duobinary CTC decoder compatible with Alteras Stratix II designs and a reference model that can be used when simulating the decoder alone or the whole signal processing chain. Some of the features of the hardware are that block sizes, puncture rates and number of iterations are dynamically configured between each block Before synthesis it is possible to choose how many decoders that will work in parallel and how many bits the soft input will be represented in. The circuit has been run in 100 MHz in the lab and that gives a throughput around 50Mbit with four decoders working in parallel. This report describes the implementation, including its development, background and future possibilities.

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