A theoretical methodology and study of charge transport through GNRs, as well as in metallic and semiconducting CNTs, with randomly distributed functional groups covalently attached to the system surface is presented. By resorting to both first principles calculations, to obtain a suitable parametrization of the electronic structure, and a fully ab initio transport approach calculation to explore conduction regimes through large and disordered systems. The quantum transport modeling is based on the Green function formalism, combining an iterative scheme for the calculation of transmission coefficients with the Landauer formula for the coherent conductance. The results describe how the conductance of the hybrid systems is altered as a function of incident electron energy and molecules coverage density. Comparing two different types of functional groups, transport regimes are explored. Phenyls and hydroxyl groups induce a local orbital rehybridization of the CNTs and GNRs anchor carbon atoms from sp2-type to sp3-type yielding a localized transport regime. On the other hand, carbene groups do not disrupt the original sp2 network of armchair and small diameter zigzag CNTs which allows for good conductance preservation.

<p>The development of integrated circuit technology seen in the last decades has enabled a large variety of battery operated equipment to emerge, such as smallsensors and medical implants. These applications often has low requirements on sampling frequency but require a very low power consumption to achieve a longbattery life.</p><p>This thesis investigates one aspect of implementing a low power and low frequency analog to digital converter (ADC) using a technique called Sigma Delta-modulation.The Sigma Delta-ADC uses few analog components but instead it requires a digital filter to extract the wanted resolution. It is this filter which is under investigation in this work.</p><p>To investigate the power consumption under the presumption that the filter would be a custom circuit implemented on-chip, a simplistic approach has been taken. Based on a high-level algorithmic investigation and the fact that it is popularly used together with Sigma Delta-modulators the Cascaded Integrator Comb (CIC) filter was chosen for implementation.</p><p>The CIC-filter uses only adders and delay elements which is a great advantage when aiming at a low power consumption. The drawback is that this filter has a poor passband which can introduce distortion within the signal band. Using the Spectre simulator provided in the Cadence Virtuoso suite the lowest power consumption achieved was 16 nW, extracting 80 % of the theoretically available resolution.</p>

<p>Captured and generated 3D data can be so large that it creates a problem for today's computers since they do not fit into the main or graphics card memory. Therefore methods for handling and rendering the data must be developed. This thesis presents a way to pre-process and render out-of-core height map data for real time use. The pre-processing uses a mesh decimation API called Simplygon developed by Donya Labs to optimize the geometry. From the height map a normal map can also be created and used at render time to increase the visual quality. In addition to the 3D data textures are also supported. To decrease the time to load an object the normal and texture maps can be compressed on the graphics card prior to rendering. Three different methods for covering gaps are explored of which one turns out to be insufficient for rendering cylindrical equidistant projected data.At render time two threads work in parallel. One thread is used to page the data from the hard drive to the main and graphics card memory. The other thread is responsible for rendering all data. To handle precision errors caused by spatial difference in the data each object receives a local origin and is then rendered relative to the camera. An atmosphere which handles views from both space and ground is computed on the graphics card.The result is an application adapted to current graphics card technology which can page out-of-core data and render a dataset covering the entire earth at 500 meters spatial resolution with a realistic atmosphere.</p>

Captured and generated 3D data can be so large that it creates a problem for today's computers since they do not fit into the main or graphics card memory. Therefore methods for handling and rendering the data must be developed. This thesis presents a way to pre-process and render out-of-core height map data for real time use. The pre-processing uses a mesh decimation API called Simplygon developed by Donya Labs to optimize the geometry. From the height map a normal map can also be created and used at render time to increase the visual quality. In addition to the 3D data textures are also supported. To decrease the time to load an object the normal and texture maps can be compressed on the graphics card prior to rendering. Three different methods for covering gaps are explored of which one turns out to be insufficient for rendering cylindrical equidistant projected data.At render time two threads work in parallel. One thread is used to page the data from the hard drive to the main and graphics card memory. The other thread is responsible for rendering all data. To handle precision errors caused by spatial difference in the data each object receives a local origin and is then rendered relative to the camera. An atmosphere which handles views from both space and ground is computed on the graphics card.The result is an application adapted to current graphics card technology which can page out-of-core data and render a dataset covering the entire earth at 500 meters spatial resolution with a realistic atmosphere.

The development of integrated circuit technology seen in the last decades has enabled a large variety of battery operated equipment to emerge, such as smallsensors and medical implants. These applications often has low requirements on sampling frequency but require a very low power consumption to achieve a longbattery life. This thesis investigates one aspect of implementing a low power and low frequency analog to digital converter (ADC) using a technique called Sigma Delta-modulation.The Sigma Delta-ADC uses few analog components but instead it requires a digital filter to extract the wanted resolution. It is this filter which is under investigation in this work. To investigate the power consumption under the presumption that the filter would be a custom circuit implemented on-chip, a simplistic approach has been taken. Based on a high-level algorithmic investigation and the fact that it is popularly used together with Sigma Delta-modulators the Cascaded Integrator Comb (CIC) filter was chosen for implementation. The CIC-filter uses only adders and delay elements which is a great advantage when aiming at a low power consumption. The drawback is that this filter has a poor passband which can introduce distortion within the signal band. Using the Spectre simulator provided in the Cadence Virtuoso suite the lowest power consumption achieved was 16 nW, extracting 80 % of the theoretically available resolution.

The filter complexity in the multi-stage decimation system of a Δ-Σ ADC increases progressively as one moves to higher stages of decimation due to the fact that the input word length of the higher stages also increases progressively. The main motivation for this thesis comes from the idea of investigating a way, to reduce the input word length in the later filter stages of the decimation system which could reduce the filter complexity. To achieve this, we use a noise-shaping loop between the first and later stages so that the input word length for the later stages remains smaller than in the case where we do not use the noise-shaping loop. However, the performance (SNR/ Noise-level) level should remain the same in both cases. This thesis aims at analyzing the implications of using a noise-shaping loop in between the decimation stages of a Δ-Σ ADC and also finding the appropriate decimation filter types that could be used in such a decimation system. This thesis also tries to compare the complexity introduced by using the noise-shaping loop with the reduction achieved in the later decimation stages in terms of the input word length. Filter required in the system will also be optimized using minimax optimization technique.

Developing a flexible receiver, which can be reconfigured to multiple standards, is the key to solving the problem of embedding numerous and ever-changing functionalities in mobile handsets. Difficulty in efficiently reconfiguring analog blocks of a receiver chain to multiple standards calls for moving the ADC as close to the antenna as possible so that most of the processing is done in DSP. Different standards are sampled at different frequencies and a programmable anti-aliasing filtering is needed here. Windowed integration samplers have an inherent sinc filtering which creates nulls at multiples of fs. The attenuation provided by sinc filtering for a bandwidth B is directly proportional to the sampling frequency fs and, in order to meet the anti-aliasing specifications, a high sampling rate is needed. ADCs operating at such a high oversampling rate dissipate power for no good use. Hence, there is a need to develop a programmable discrete-time down-sampling circuit with high inherent anti-aliasing capabilities. Currently existing topologies use large numbers of switches and capacitors which occupy a lot of area.A novel technique in reducing die area on a discrete-time sinc2 ↓2 filter for charge sampling is proposed. An SNR comparison of the conventional and the proposed topology reveals that the new technique saves 25 percent die area occupied by the sampling capacitors of the filter. The proposed idea is also extended to implement higher downsampling factors and a greater percentage of area is saved as the down-sampling factor is increased. The proposed filter also has the topological advantage over previously reported works of allowing the designers to use active integration to charge the capacitance, which is critical in obtaining high linearity. A novel technique to implement a discrete-time sinc3 ↓2 filter for windowed integration samplers is also proposed. The topology reduces the idle time of the integration capacitors at the expense of a small complexity overhead in the clock generation, thereby saving 33 percent of the die area on the capacitors compared to the currently existing topology. Circuit Level simulations in 45 nm CMOS technlogy show a good agreement with the predicted behaviour obtained from the analaysis.

<p>This work presents the design and implementation of a decimation filter for a three bits sigma delta analog to digital converter. The input is audio with a oversampling ratio of 32. Filter optimization and tradeoffs concerning the design is described. The filter is a multistage filter consisting of two cascaded FIR filters. The arithmetic unit is a multi-precision unit that can handle three or 24 bits MAC operations. The designed decimation filter is synthesized on standard cells of a 0.13 μm CMOS library.</p>

This work presents the design and implementation of a decimation filter for a three bits sigma delta analog to digital converter. The input is audio with a oversampling ratio of 32. Filter optimization and tradeoffs concerning the design is described. The filter is a multistage filter consisting of two cascaded FIR filters. The arithmetic unit is a multi-precision unit that can handle three or 24 bits MAC operations. The designed decimation filter is synthesized on standard cells of a 0.13 μm CMOS library.

An exploratory research project was conducted through a company focusing on CAD and their own developed real-time 3D model viewer. The company needed to be able to convert CAD models to use in Unreal Engine with great visual quality. Before this project, another was conducted to perform the simple conversion of CAD models to the FBX file format, which Unreal uses. In extension to the previous project, one needed to add functionalities to manipulate the models for better quality and performance. The tasks were carried out and performed with good results.