Through linguistic abilities, our brain can comprehend and produce an infinite number of new sentences constructed from a finite set of words. Although recent research has uncovered the neural representation of semantics during comprehension of isolated words or adjective-noun phrases, the neural representation of the words during utterance planning is less understood. We apply existing machine learning methods to Magnetoencephalography (MEG) data recorded during a picture naming experiment, and predict the semantic properties of uttered words before they are said. We explore the representation of concepts over time, under controlled tasks, with varying compositional requirements. Our results imply that there is enough information in brain activity recorded by MEG to decode the semantic properties of the words during utterance planning. Also, we observe a gradual improvement in the semantic decoding of the first uttered word, as the participant is about to say it. Finally, we show that, compared to non-compositional tasks, planning to compose an adjective-noun phrase is associated with an enhanced and sustained representation of the noun. Our results on the neural mechanisms of basic compositional structures are a small step towards the theory of language in the brain. / Graduate

<p>A forward error correction technique known as convolutional coding with Viterbi decoding was explored in this final thesis. This Viterbi project is part of the baseband Error control project at electrical engineering department, Linköping University.</p><p>In this project, the basic Viterbi decoder behavior model was built and simulated. The convolutional encoder, puncturing, 3 bit soft decision, BPSK and AWGN channel were implemented in MATLAB code. The BER was tested to evaluate the decoding performance.</p><p>The main issue of this thesis is to implement the RTL level model of Viterbi decoder. With the testing results of behavior model, with minimizing the data path, register size and butterflies in the design, we try to achieve a low silicon cost design. The RTL Viterbi decoder model includes the Branch Metric block, the Add-Compare-Select block, the trace-back block, the decoding block and next state block. With all done, we further understand about the Viterbi decoding algorithm and the DSP implementation methods.</p>

Iterative decoding and codes on graphs were first devised by Gallager in 1960, and then rediscovered by Berrou, Glavieux and Thitimajshima in 1993. This technique plays an important role in modern communications, especially in coding theory and practice. In particular, low-density parity-check (LDPC) codes, introduced by Gallager in the 1960s, are the class of codes at the heart of iterative coding. Since these codes are quite general and exhibit good performance under message-passing decoding, they play an important role in communications research today. A thorough analysis of iterative decoding systems and the relationship between maximum a posteriori (MAP) and belief propagation (BP) decoding was initiated by Measson, Montanari, and Urbanke. This analysis is based on density evolution (DE), and extrinsic information transfer (EXIT) functions, introduced by ten Brink. Following their work, this thesis considers the MAP decoding thresholds of three iterative decoding systems. First, irregular repeat-accumulate (IRA) and accumulaterepeataccumulate (ARA) code ensembles are analyzed on the binary erasure channel (BEC). Next, the joint iterative decoding of LDPC codes is studied on the dicode erasure channel (DEC). The DEC is a two-state intersymbol-interference (ISI) channel with erasure noise, and it is the simplest example of an ISI channel with erasure noise. Then, we introduce a slight generalization of the EXIT area theorem and apply the MAP threshold bound for the joint decoder. Both the MAP and BP erasure thresholds are computed and compared with each other. The result quantities the loss due to iterative decoding Some open questions include the tightness of these bounds and the extensions to non-erasure channels.

Multiple Input Multiple Output (MIMO) systems are a key technology for next generation high speed wireless communication standards like 802.11n, WiMax etc. MIMO enables spatial multiplexing to increase channel bandwidth which requires the use of multiple antennas in the receiver and transmitter side. The increase in bandwidth comes at the cost of high silicon complexity of MIMO detectors which result, due to the intricate algorithms required for the separation of these spatially multiplexed streams. Previous implementations of MIMO detector have mainly dealt with the issue of complexity reduction, latency minimization and throughput enhancement. Although, these detectors have successfully mapped algorithms to relatively simpler circuits but still, latency and throughput of these systems need further improvements to meet standard requirements. Additionally, most of these implementations don’t deal with the requirements of reconfigurability of the detector to multiple modulation schemes and different antennae configurations. This necessary requirement provides another dimension to the implementation of MIMO detector and adds to the implementation complexity. This thesis focuses on the efficient VLSI implementation of the MIMO detector with an emphasis on performance and re-configurability to different modulation schemes. MIMO decoding in our detector is based on the fixed sphere decoding algorithm which has been simplified for an effective VLSI implementation without considerably degrading the near optimal bit error rate performance. The regularity of the architecture makes it suitable for a highly parallel and pipelined implementation. The decoder has intrinsic traits for dynamic re-configurability to different modulation and encoding schemes. This detector architecture can be easily tuned for high/low performance requirements with slight degradation/improvement in Bit Error Rate (BER) depending on needs of the overlying application. Additionally, various architectural optimizations like pipelining, parallel processing, hardware scheduling, dynamic voltage and frequency scaling have been explored to improve the performance, energy requirements and re-configurability of the design.

Our main objective in this thesis is to study the effect of narrow band interference on OFDM systems operating in the 2.4 Ghz ISM band and identify ways to improve upon existing techniques to deal with them. We first consider how narrow band signals interfere with OFDM systems. Various noise variance estimation and signal to noise ratio estimation techniques for OFDM systems are then discussed. We also study the conventional Viterbi Algorithm that is used in OFDM wireless systems and the proposed modifications to it in the literature. Our main contribution is a detailed experimental analysis of a modified Viterbi Algorithm that outperforms the conventional one in the presence of narrow band interference. Interference samples captured using a wireless hardware platform were used in simulation to test this modified algorithm. From our analysis we realize that in the presence of narrow band frequency selective interference (such as Bluetooth), the conventional Viterbi Algorithm can be modified to improve the performance of OFDM systems.

Our main objective in this thesis is to study the effect of narrow band interference on OFDM systems operating in the 2.4 Ghz ISM band and identify ways to improve upon existing techniques to deal with them. We first consider how narrow band signals interfere with OFDM systems. Various noise variance estimation and signal to noise ratio estimation techniques for OFDM systems are then discussed. We also study the conventional Viterbi Algorithm that is used in OFDM wireless systems and the proposed modifications to it in the literature. Our main contribution is a detailed experimental analysis of a modified Viterbi Algorithm that outperforms the conventional one in the presence of narrow band interference. Interference samples captured using a wireless hardware platform were used in simulation to test this modified algorithm. From our analysis we realize that in the presence of narrow band frequency selective interference (such as Bluetooth), the conventional Viterbi Algorithm can be modified to improve the performance of OFDM systems.

This thesis studies advanced error control schemes using turbo-like codes, turbo-like coded modulations, turbo hybrid-ARQ (Automatic Repeat reQuest) schemes, and rate compatible puncturing techniques for reliable and adaptive commercial and tactical spread-spectrum communications, especially for code-division multiple access (CDMA) cellular systems and direct-sequence (DS) and frequency-hopping (FH) anti-jam systems. Furthermore, we utilize both the maximum-likelihood (ML) bounding techniques and convergence analysis to design and analyze various turbo-like coding schemes that show different behaviors in error performance from conventional trellis coding schemes. In the area of DS-CPM, we propose a DS concatenated coded CPM system for pulse-noise jamming channels and an anti-jam iterative receiver utilizing jammer state information. We also design a mixed concatenated CPM system that mixes CPM schemes with different convergence characteristics. In addition, we present the ML bound and convergence analysis for the jamming channel. In the area of FH-CPM, we propose anti-jam serially concatenated slow FH-CPM systems, whose phase is continuous during each hop interval, along with coherent and non-coherent iterative receivers. We also propose an iterative jamming estimation technique for the iterative receiver. In the area of multi-h CPM, we propose a power- and bandwidth-efficient serially concatenated multi-h CPM along with an appropriate iterative receiver structure. Serially concatenated multi-h CPM is shown to outperform single-h CPM. To design adaptive and versatile error control schemes using turbo-like codes for packet-data networks, we propose turbo hybrid-ARQ (HARQ) and rate compatible puncturing techniques for retransmission. In the area of turbo hybrid-ARQ, we propose a Type-I turbo HARQ scheme using a concatenated RS-turbo code and a packet combining technique for W-CDMA system to improve the performance of error and decoding latency. The W-CDMA system including the fast power control and coherent Rake receiver with a channel estimation technique for multipath fading channels is considered. Finally, in the area of rate compatible punctured turbo-like codes, we propose rate compatible punctured turbo (RCPT) codes and rate compatible punctured serially concatenated convolutional (RCPS) codes along with their puncturing methods. In addition, we propose Type-II RCPT-HARQ and RCPS-HARQ schemes to perform an efficient incremental redundancy retransmission.

Iterative decoding and codes on graphs were first devised by Gallager in 1960, and then rediscovered by Berrou, Glavieux and Thitimajshima in 1993. This technique plays an important role in modern communications, especially in coding theory and practice. In particular, low-density parity-check (LDPC) codes, introduced by Gallager in the 1960s, are the class of codes at the heart of iterative coding. Since these codes are quite general and exhibit good performance under message-passing decoding, they play an important role in communications research today. A thorough analysis of iterative decoding systems and the relationship between maximum a posteriori (MAP) and belief propagation (BP) decoding was initiated by Measson, Montanari, and Urbanke. This analysis is based on density evolution (DE), and extrinsic information transfer (EXIT) functions, introduced by ten Brink. Following their work, this thesis considers the MAP decoding thresholds of three iterative decoding systems. First, irregular repeat-accumulate (IRA) and accumulaterepeataccumulate (ARA) code ensembles are analyzed on the binary erasure channel (BEC). Next, the joint iterative decoding of LDPC codes is studied on the dicode erasure channel (DEC). The DEC is a two-state intersymbol-interference (ISI) channel with erasure noise, and it is the simplest example of an ISI channel with erasure noise. Then, we introduce a slight generalization of the EXIT area theorem and apply the MAP threshold bound for the joint decoder. Both the MAP and BP erasure thresholds are computed and compared with each other. The result quantities the loss due to iterative decoding Some open questions include the tightness of these bounds and the extensions to non-erasure channels.

Multiple-input multiple-output (MIMO) is a well-known technique for efficiently increasing bandwidth utilization. However, the implementation of the MIMO receiver with a reasonable hardware cost is a big challenge. Most MIMO receivers exploit minimum mean-square error (MMSE), zero-forcing (ZF) and maximum-likelihood (ML) to detect MIMO signals. Among the detectors, the ZF detector is simple detector with low computational complexity, but lower performance compared to ML decoder, which has huge computational complexity. If the K-Best sphere decoding algorithm (SDA) is adopted, the system complexity can be substantially reduced and the performance can approach that of the ML scheme when the value K is sufficiently large. In this paper, a hard-output MIMO detector is implemented using the K-Best SDA for 4¡Ñ4 64-quadrature amplitude modulation (QAM) MIMO detection. The implementation is realized by using a 0.18-£gm CMOS technology. The implementation chip core area is 3.35mm2 with 229K gates, and the decoding throughput is up to 3.12Mb/s with a 25MHz clock rate.

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