The growing demand of “System on a Chip” applications necessitates integration of multiple devices on the same chip. Analog to Digital conversion is essential to interfacing digital systems to external devices such as sensors. This presents a difficulty since high precision analog devices do not mix well with high speed digital circuits. The digital environment constraints put demand on the analog portion to be resource efficient and noise tolerant at the same time. Even more demanding, Analog to Digital converters must consume a small amount of power since “System on a Chip” circuits often target portable applications. Analog to digital conversion based on Delta Sigma modulation offers an optimal solution to the above problems. It is based on digital signal processing theory and offers benefits such as small footprint, high precision, noise de-sensitivity, and low power consumption. This thesis presents a methodology for designing low power Delta Sigma modulators using a combination of modern circuit design techniques. The developed techniques have resulted in several modulators that satisfy the initial design parameters. We applied this method to design three different modulators in the 0.35um digital CMOS technology with a 3.3V supply voltage. A first order Self-Referenced modulator has a resolution of 8 bits and the lowest power consumption at 75 uW. The most successful design is the second order Self Referenced modulator that produces 12 bits of resolution with a power consumption of 87 uW. A second order Floating Gate modulator possesses features for high noise rejection, and produces 10 bits of resolution while consuming 276 uW. It is concluded that self-referenced modulators dissipate less power and offer higher performance as compared more complicated circuits such as the floating gate modulator. / Master of Science

This dissertation presents a comprehensive design and analysis framework for system-on-a-chip analog-to-digital conversion design. The design encompasses a broad class of systems, which take advantage of system-on-a-chip complexity. This class is exemplified by an interferometric photodetector array based bio-optoelectronic sensor that is built and tested as part of the reported work. While there have been many discussions of the technical details of individual analog-to-digital converter (ADC) schemes in the literature, the importance of the analog front-end as a pre-processor for a data converter and the generalized analysis including converter encoding and decoding functions have not previously been investigated thoroughly, and these are key elements in the choice of converter designs for low-noise systems such as bio-optoelectronic sensors. Frequency domain analog front-end models of ADCs are developed to enable the architectural modeling of ADCs. The proposed models can be used for ADC statistically worst-case performance estimation, with stationary random process assumptions on input signals. These models prove able to reveal the architectural advantages of a specific analog-to-digital converter schemes quantitatively, allowing meaningful comparisons between converter designs. The modeling of analog-to-digital converters as communication channels and the ADC functional analysis as encoders and decoders are developed. This work shows that analog-to-digital converters can be categorized as either a decoder-centered design or an encoder-centered design. This perspective helps to show the advantages of nonlinear decoding schemes for oversampling noise-shaping data converters, and a new nonlinear decoding algorithm is suggested to explore the optimum solution of the decoding problem. A case study of decoder-centered and encoder-centered data converter designs is presented by applying the proposed theoretical framework. The robustness and flexibility of the resulting analog-to-digital converters are demonstrated and compared. The electrical and optical sensitivity measurements of a fabricated oversampling noise shaping analog-to-digital converter circuit are provided, and a sensor system-on-a-chip using these ADCs with integrated interferometric waveguides for bio-optoelectronic sensing is demonstrated.

In this research an approach to all optical delta sigma modulator (ADSM) has been elaborated. Two important components of ADSM; "leaky integrator" and "inverted bi-stable quantizer" were modeled, on the basis of cross gain modulation of the Semiconductor Optical Amplifier (SOA). The simulations (via VPI photonics) were all in micrometer scale (suitable for chip fabrication). By simulating each element of ADSM the whole circuit was simulated and results have been showed and analyzed. By investigating the ADSM, the limiting factor for reaching higher frequencies (THz) was recognized to be the quantization device. Thus a new optical switch was introduced, for the first time so called "proteresis." By applying proteretic bi-stable device in the delta sigma modulator, the resonance frequency was improved minimum two fold from 295MHz to 575MHz without making any change in hysteretic bi-stable switch. The broad impact of this research is on the digital technologies that can be utilized in high-speed signal processing. The prime examples are the RF technologies used in military and civilian applications. Furthermore introduction of proteresis opens a new research gate for compensating delay in almost every system.

Abstract Oversampling data converters based on Delta-Sigma modulation are a popular solution for modern high-resolution applications. In the design of digital-to-analog or analog-to-digital Delta-sigma converters there are common obstacles due to the difficulties on predicting and verifying their performance. Being a highly nonlinear system, a Delta-Sigma modulator’s (DSM) quantization noise and therefore the spurious tones are difficult to analyze and predict. Multi-bit DACs can be used to improve the performance and linearize the behavior of DSMs. However, this will give rise to the need for linearizing the multi-bit DAC. A popular DAC linearization method, data weighted averaging (DWA) shapes the DAC mismatch noise spectrum. There are many variants of DWA, for low-pass and band-pass DSMs. This thesis proposes a generalization which integrates a few published variants into one, broader DWA scheme. The generalization enables expanding the tone-suppression studies into a larger concept. The performance of one- or multibit DSMs is usually verified by simulations. This thesis proposes a simulation-based qualification (characterization) method that can be used to repeatedly verify and compare the performance of multibit DSM with a DAC mismatch shaping or scrambling scheme. The last contribution of this thesis is a very simple model for tonal behavior. The model enables accurate prediction of spurious tones from both DSMs and DWA-DACs. The model emulates the tone behavior by its true birth-mechanism: frequency modulation. The proposed prediction model for tone-behavior can be used for developing new tone-cancelation methods. Based on the model, a DWA linearization method is also proposed. / Tiivistelmä Delta-Sigma modulaatio on suosituin tekniikka ylinäytteistävissä datan muuntimissa. Riippumatta toteutustarkoituksesta (analogia-digitaali- tai digitaali-analogia-muunnos), Delta-Sigma (DS) modulaatiossa on yleisesti tunnettuja käyttäytymisen ennustamiseen liittyviä ongelmia. Nämä ongelmat ovat peräisin modulaattorin luontaisesta epälineaarisuudesta: DS-muunnin on nimittäin vahvasti epälineaarinen takaisinkytketty systeemi, jonka harhatoistojen ennustaminen ja analysointi on erittäin hankalaa. Yksibittisestä monibittiseen DS-muuntimeen siirryttäessä muuntimen suorituskyky paranee, ja muuntimen kohinakäyttäytyminen on lineaarisempaa. Tämä kuitenkin kostautuu tarpeena linearisoida DS-muuntimen digitaali-analogia (D/A) muunnin. Tällä hetkellä tunnetuin linearisointimenetelmä on nimeltään DWA (data weighted averaging) algoritmi. Tässä työssä DWA:lle ja sen lukuisille varianteille esitellään eräänlainen yleistys, jonka avulla algoritmia voidaan soveltaa sekä alipäästö- että kaistanpäästö-DS-muuntimelle. Kuten tunnettua, DS-modulaattorin analyyttinen tarkastelu on raskasta. Yksi- ja monibittisten DS-muuntimien suunnitellun käyttäytymisen varmistaminen tapahtuukin yleensä simulointien avulla. Työssä esitetään simulointiperiaate, jolla voidaan kvalifioida (karakterisoida) monibittinen DS-muunnin. Tarkemmin, kvalifioinnin kohteena on DWA:n kaltaiset D/A -muuntimien linearisointimentelmät. Kyseessä on pyrkimys ennen kaikkea toistettavaan menetelmään, jolla eri menetelmiä voidaan verrata nopeasti ja luotettavasti. Tämän väitöstyön viimeinen kontribuutio on matemaattinen malli harhatoistojen syntymekanismille. Mallilla sekä DS-muunnoksen että DWA-D/A -muunnokseen liittyvät harhatoistot voidaan ennustaa tarkasti. Harhatoistot mallinnetaan yksinkertaisella havaintoihin perustuvalla FM-modulaatiokaavalla. Syntymekanismin mallinnus mahdollistaa DS-muuntimien ennustettavuuden ja täten auttaa harhatoiston kumoamismenetelmien kehittämistä. Työssä esitetään yksi matemaattisen mallin avulla kehitetty DWA-D/A -muunnoksen linearisointimenetelmä.

In this theses techniques for high-speed digital delta-sigma modulator(DDSM) structures are considered. Four techniques are applied andevaluated: unfolding, increasing the number of delay elements in theinner loop, pipelining/retiming, and optimizations provided by thesynthesis tool. Of interest is to see the speed-area-power trade-offs.For implementation, three different modulators meeting the samerequirements are implemented. Each modulator has a 16-bit input andresults in a 3-bit output. The baseline case is a second-ordermodulator, which has one delay element in its inner loop. Throughoptimization, two new structures are found: to provide two delayelements in the inner loop, a fourth-order modulator is required,while to provide three delay elements, a thirteenth-order modulator isobtained.The results show that in general it is better to unfold the modulatorthan to obtain the speed-up through optimizing the arithmeticoperators with the synthesis tool. Using correct pipelining/retimingis also crucial. Finally, for very high-speed implementation, usingthe structures with more delay elements is required. Also, in manycases these are more area and power efficient compared to usingoptimized arithmetic operators, despite their higher computationalcomplexity.

International Telemetering Conference Proceedings / October 26-29, 1992 / Town and Country Hotel and Convention Center, San Diego, California / For research purposes on helicopter rotor acoustics a large data acquisition system called TEDAS (Transputer based Expandable Data Acquisition System) has been developed. The key features of this system are: unlimited expandability and sum data rate, local storage of data during operation, very simple analog anti aliasing filtering due to extensive digital filtering, and integrated computational power which scales with the number of channels. The sample rate is up to 50 kHz/channel, the resolution is 16 bit, 360 channels are realized now. TEDAS consists of blocks with 8 A/D converters which are controlled by one transputer T800. The size of the local memory is 4 Mbyte. Any number of blocks (IDAM = Intelligent Data Acquisition Module) can be combined to a complete system. Data preprocessing is done in parallel inside the IDAMs. As for 16 bit systems the analog antialiasing filtering becomes a dominant factor of the costs, delta sigma ADCs with oversampling and internal digital filtering are used. This produces an exact linear phase and a stop band rejection of -90 dB.

International Telemetering Conference Proceedings / October 17-20, 1988 / Riviera Hotel, Las Vegas, Nevada / A switched-capacitor technique for realization of one bit serial A/D converter is presented. A conversion accuracy that is higher than 15 bits can be expected from its integrated realization. Results of simulation are presented. It is shown that arithmetic operations on bit serial signals are possible. Using arithmetic operations on delta-modulated signals, it is possible to build inexpensive options necessary in instrumentation.

This dissertation explores methods of reducing the oversampling ratio (OSR) of both delta-sigma modulators and incremental data converters. The first reduced-OSR architecture is the high-order cascaded delta-sigma modulator. These delta-sigma modulators are shown to reduce the in-band noise sufficiently at OSRs as low as 3 while providing power savings. The second low OSR architecture is the high-order cascaded incremental data converter which possesses signal-to-quantization noise ratio (SQNR) advantages over equivalent delta-sigma modulators at low OSRs. The final architecture is the time-interleaved incremental data converter where two designs are identified as potential methods of increasing the throughput of low OSR incremental data converters. A prototype chip is designed in 0.18um CMOS technology which can operate in three modes by simply changing the resetting clock phases. It can operate as an 8-stage pipeline analog-to-digital (A/D) converter, an 8th-order cascaded delta-sigma modulator, and an 8th-order cascaded incremental data converter with an OSR of 3.

For the fractional-N frequency synthesizers using delta-sigma modulation (DSM) techniques, higher PLL bandwidth is highly desirable in order to achieve faster settling time. As the PLL bandwidth is increased, more quantization noises pass through the PLL so that the output phase noise performance is degraded. There is a tradeoff between phase-noise performance and PLL bandwidth. To improve the problem, the thesis studies the quantization noise cancellation technique. With this technique, the PLL bandwidth can be increased without the cost of degrading phase-noise performance. With the help of Agilent EEsof¡¦s ADS, the phase-noise performance of the studied fractional-N frequency synthesizers can be predicted. For demonstration, this research implements a 2.6 GHz fractional-N frequency synthesizer hybrid module, and compares the measured phase noises with and without the technique under considering various combinations of MASH DSM orders and PLL bandwidth. Another demonstration of this thesis is to design a PLL IC using TSMC 0.18 £gm CMOS process, and make a discussion on the testing performance of the PLL IC.

In present day, digital signal processing (DSP) is a popular technology and widely used in many fields. There have increasing number of applications that need high resolution converters. Therefore, analog-to-digital converters play a major role in DSP, and a well-performed ADC will enhance the performance of a certain system. Different types of ADCs are available for various functions. Delta-sigma  converters are famous for high resolution. Dynamic parameters can be used to judge the performance of an ADC, this paper will focus on the critical parameters of spectrum analysis, which contains Signal-to-Noise-and-Distortion Ratio (SINAD), Effective Number of Bits (ENOB) and Spurious-free Dynamic Range (SFDR). The theory and test method of these critical parameters are proposed in this paper using the Evaluation Module and Matlab. The results we acquired from the Evaluation Module are SINAD=86.15dB, SFDR=109.2dB, ENOB=14.177bits; and the results we calculated from MATLAB are: SINAD=86.14dB, SFDR=108.8dB, ENOB=14bits.