Delta-sigma analog-to-digital converters traditionally have been used for low speed, high resolution applications such as measurements, sensors, voice and audio systems. Through continued device scaling in CMOS technology and architectural and circuit level design innovations, they have even become popular for wideband, high dynamic range applications such as wired and wireless communication systems. Therefore, power efficient wideband low power delta-sigma data converters that bridges analog and digital have become mandatory for popular mobile applications today. In this dissertation, two architectural innovations and a development and realization of a state-of-the-art delta-sigma analog to digital converter with effective design techniques in both architectural and circuit levels are presented. The first one is timing-relaxed double noise coupling which effectively provides 2nd order noise shaping in the noise transfer function and overcomes stringent timing requirement for quantization and DEM. The second one presented is a noise shaping SAR quantizer, which provides one order of noise shaping in the noise transfer function. It uses a charge redistribution SAR quantizer and is applied to a timing-relaxed lowdistortion delta-sigma modulator which is suitable for adopting SAR quantizer. Finally a cascade switched capacitor delta-sigma analog-to-digital converter suitable for WLAN applications is presented. It uses a noise folding free double sampling technique and an improved low-distortion architecture with an embedded-adder integrator. The prototype chip is fabricated with a double poly, 4 metal, 0.18μm CMOS process. The measurement result achieves 73.8 dB SNDR over 10 MHz bandwidth. The figure of merit defined by FoM = P/(2 x BW x 2[superscript ENOB]) is 0.27 pJ/conv-step. The measurement results indicate that the proposed design ideas are effective and useful for wideband, low power delta-sigma analog-to-digital converters with low oversampling ratio. / Graduation date: 2012 / Access restricted to the OSU Community at author's request from June 19, 2012 - June 19, 2013

<p>Many medical, environmental, and industrial control applications rely on wide-dynamic-range sensors and A/D converter systems. For most photo-detector-based applications, the input-current is integrated onto a capacitor, either with a variable time, or a variable capacitor value, followed by a sample-and-hold and a voltage A/D converter. The penalty for achieving wide-dynamic-range with the above approach is power and circuit complexity. </p><p>We propose to use the unique properties of current-input continuous-time Delta-Sigma A/D converters to combine the photo-detector current-integration with simultaneous wide-dynamic-range A/D conversion, using programmable reference currents and programmable clock frequencies. </p><p>A programmable current-input wide-dynamic-range Delta-Sigma A/D converter is designed and fabricated using MOSIS AMI 1.5 um 5 V CMOS process. The programmable A/D converter test results exhibit a consistent 12-bit resolution over the programmability range of the reference-currents, from 17.2 nA to 4.4 uA. The supply-current varies from 60 uA to 240 uA, whereas the A/D converter sample-rates increase from 4 Samples/s to 1 kSamples/s, achieving an overall system-dynamic-range of 20-bits. </p><p>An RF-powered version is designed and fabricated using MOSIS ON 0.5 um 3 V CMOS process. It is designed to work at 128 Samples/s to 11.25 kSamples/s sample-rates, achieving 12-bit resolution with only 128 oversampling ratio. The A/D converter supply-current is designed to range from 10 uA to 70 uA to allow its integration with an RF-power source. The RF-powered version of the programmable Delta-Sigma A/D converter includes an on-chip voltage regulator that generates a stable 3 V DC-voltage, and consumes only 15 uA current.</p> / Dissertation

This thesis strives to enhance the performance of delta-sigma modulators in two areas: increasing their speed and enabling their operation in a low voltage environment. Parallelism based on time-interleaving can be used to increase the speed of delta-sigma modulators. A novel single-path time-interleaved architecture is derived and analyzed. Finite opamp gain and bandwidth result in a mismatch between the noise transfer functions of the internal quantizers which degrades the performance of the new modulator. Two techniques are presented to mitigate the mismatch problem: a hybrid topology where the first stage uses multiple integrators while the rest of the modulator uses a single path of integrators and a digital calibration method. The input-feedforward technique removes the input-signal component from the internal nodes of delta-sigma modulators. The removal of the signal component reduces the signal swing and distortion requirements for the opamps. These characteristics enable the reliable implementation of delta-sigma modulators in modern CMOS technology. Two implementation issues for modulators with input-feedforward are considered. First, the drawback of the analog adder at the quantizer input is identified and the capacitive input feedforward technique is introduced to eliminate the adder. Second, the double sampled input technique is proposed to remove the critical path generate by the input feedforward path. Novel input-feedforward delta-sigma architecture is proposed. The new digital input feedforward (DIFF) modulator maintains the low swing and low distortion requirements of the input feedforward technique, it eliminates the analog adder at the quantizer input, and it improves the achievable resolution. To demonstrate these advantages, a configurable delta-sigma modulator which can operate as a feedback topology or in DIFF mode is implemented in 0.18μm CMOS technology. Both modulators operate at 20MHz clock with an oversampling ratio of 8. The power consumption in the DIFF mode is 22mW and in feedback mode is 19mW. However, the DIFF mode achieves a peak SNDR of 73.7dB (77.1dB peak SNR) while the feedback mode achieves a peak SNDR of 64.3dB (65.9dB peak SNR). Therefore, the energy required per conversion step for the DIFF architecture (2.2 pJ/step) is less than half of that required by the feedback architecture (5.7 pJ/step).

Most present day implementations of delta-sigma modulators are discrete-time ones using switched-capacitor circuits. A resistor-capacitor (RC) implementation of a delta-sigma analog to digital converter (ADC) does not use switched capacitor (SC) technology. While SC implementation has the advantages of being discrete-time, no resistors used and improved stability control, RC implementation has the advantage of no switches being used (other than quantizer) and therefore a simpler circuit implementation. Continuous-time implementations can achieve lower thermal noise levels than switched capacitor modulators. Butterworth Multi-stage Noise Shaping (MASH) architecture is one of the promising architectures to implement in continuous-time domain. For a convenient design and quantization noise spectrum shaping of a delta sigma data converter, it's highly desirable for the Noise Transfer Function (NTF) to take the form of a high-pass filter. The MASH architecture was introduced to overcome stability problems commonly faced beyond a second order structure. Delta-sigma data converters are new converter designs that are preferred for integrated circuits and for high-resolution applications. It is highly desirable for the NTF of delta-sigma data converters to take the form of conventional highpass filters for convenient design purposes and shaping of the quantization noise spectrum. However, conventional delta-sigma architectures allow for only low orders and very low cutoff frequencies for such highpass filters, otherwise the converter becomes unstable. In previous projects it was found that a MASH implementation (each stage being second order) of a delta-sigma data converter where the NTF of each stage is a Butterworth highpass filter holds much promise. This current project is to accomplish RC implementation of fourth-order Butterworth MASH delta-sigma data converter. The circuit design procedure will be shown, starting with the desired NTF characteristics, and yielding the required parameters for the RC integrators with gains that are determined from the desired transfer function. The circuit simulation, yielding the bit stream frequency spectrum and the signal to noise ratio, will be based on Mentor Graphics Eldo SPICE simulations. The performance and characteristics of the circuit is fully analyzed and documented for a wide variety of variations and test conditions. / Thesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical and Computer Engineering. / "August 2006." / Includes bibliographic references (leaves 41-43).

Delta sigma data converters have found to be of greater interest for almost 40 years now. Continuous time implementation of these converters, especially for high speed and low power applications has been very challenging. Here in this thesis we have discussed Resistor Capacitor (RC) implementation of Chebyshev Type II high pass Noise Transfer Function (NTF). RC implementation has its own advantages compared to that of a Switched Capacitor (SC) circuit. While SC implementation has the advantages of being discrete-time, no resistors used, and improved stability control, RC implementation has the advantage of no switches being used (other than the quantizer) and therefore a simpler circuit implementation. In this thesis the details of the design and analysis of a fourth order RC delta sigma data converter will be given. The NTF is that of a fourth-order Chebyshev Type II highpass filter, where the noise is high passed and removed using a low pass filter and the signal remains constant across the low frequency band. The circuit implementation consists of four RC integrators with gain stages that are determined from the desired transfer function. The feedback loop includes of a sample and hold circuit followed by a one-bit quantizer: these are the only nonlinear elements in the circuit design. The circuit design procedure will be given, starting with the desired NTF characteristics, and yielding the required gain parameters for the four integrator circuit architecture, obtained to implement the requiredH(s). MATLAB is used for easy computation. The circuit simulation, yielding the bit stream frequency spectrum and the signal to noise ratio, will be based on Mentor Graphics Eldo SPICE simulations. The overall performance achieves the equivalent of 11 bits. This is obtained from a fourth order circuit, using RC implementation. / Thesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical and Computer Engineering. / Includes bibliographical references (leaves 37-38) / "December 2006."

This thesis strives to enhance the performance of delta-sigma modulators in two areas: increasing their speed and enabling their operation in a low voltage environment. Parallelism based on time-interleaving can be used to increase the speed of delta-sigma modulators. A novel single-path time-interleaved architecture is derived and analyzed. Finite opamp gain and bandwidth result in a mismatch between the noise transfer functions of the internal quantizers which degrades the performance of the new modulator. Two techniques are presented to mitigate the mismatch problem: a hybrid topology where the first stage uses multiple integrators while the rest of the modulator uses a single path of integrators and a digital calibration method. The input-feedforward technique removes the input-signal component from the internal nodes of delta-sigma modulators. The removal of the signal component reduces the signal swing and distortion requirements for the opamps. These characteristics enable the reliable implementation of delta-sigma modulators in modern CMOS technology. Two implementation issues for modulators with input-feedforward are considered. First, the drawback of the analog adder at the quantizer input is identified and the capacitive input feedforward technique is introduced to eliminate the adder. Second, the double sampled input technique is proposed to remove the critical path generate by the input feedforward path. Novel input-feedforward delta-sigma architecture is proposed. The new digital input feedforward (DIFF) modulator maintains the low swing and low distortion requirements of the input feedforward technique, it eliminates the analog adder at the quantizer input, and it improves the achievable resolution. To demonstrate these advantages, a configurable delta-sigma modulator which can operate as a feedback topology or in DIFF mode is implemented in 0.18μm CMOS technology. Both modulators operate at 20MHz clock with an oversampling ratio of 8. The power consumption in the DIFF mode is 22mW and in feedback mode is 19mW. However, the DIFF mode achieves a peak SNDR of 73.7dB (77.1dB peak SNR) while the feedback mode achieves a peak SNDR of 64.3dB (65.9dB peak SNR). Therefore, the energy required per conversion step for the DIFF architecture (2.2 pJ/step) is less than half of that required by the feedback architecture (5.7 pJ/step).

<p>A full custom integrated circuit design of a serial bitstream processor is proposed for remote smart sensor systems. This dissertation describes details of the architectural exploration, circuit implementation, algorithm simulation, and testing results. The design is fabricated and demonstrated to be a successful working processor for basic algorithm functions. In addition, the energy performance of the processor, in terms of energy per operation, is evaluated. Compared to the multi-bit sensor processor, the proposed sensor processor provides improved energy efficiency for serial sensor data processing tasks, and also features low transistor count and area reduction advantages.</p><p>Operating in long-term, low data rate sensing environments, the serial bitstream processor developed is targeted at low-cost smart sensor systems with serial I/O communication through wireless links. This processor is an attractive option because of its low transistor count, easy on-chip integration, and programming flexibility for low data duty cycle smart sensor systems, where longer battery life, long-term monitoring and sensor reliability are critical. </p><p>The processor can be programmed for sensor processing algorithms such as delta sigma processor, calibration, and self-test algorithms. It also can be modified to utilize Coordinate Rotation Digital Computer (CORDIC) algorithms. The applications of the proposed sensor processor include wearable or portable biomedical sensors for health care monitoring or autonomous environmental sensors.</p> / Dissertation

The thesis proposes an integrator with an OPAMP in the feedback loop to fulfill 1MHz bandwidth SI Sigma Delta modulator. The OPAMP is used to pull down the input impedance and get high speed and high resolution. Oversampling and noise shaping are the two keys of Sigma Delta modulator. In structure, multistage is helpful for depressing noises and we use three stages to fulfill this 4-order proposed Sigma Delta modulator. The proposed Sigma Delta modulator uses TSMC 0.18£gm CMOS process and it is a 4-order and three stages SI Sigma Delta modulator. The sampling rate is 32MHz, bandwidth is 1MHz, and oversampling ratio is 16.

This paper presents a distributed feedback and feedforward of discrete-time delta sigma modulator applications in the radio. We know the delta-sigma modulator using oversampling and noise shaping technique, thus we can relax the specifications of the components. This paper described the architectural differences and compare, the in-band signal is less sensitive to noise interference, and improve the resolution of the circuit. In the resonator, a simple structure with a small number of capacitor in resonator circuit. This paper uses the TSMC 0.18£gm process parameters to the simulation, implementation, and measurement. Our fourth-order discrete-time delta-sigma modulator specifications as follows: the input signal frequency is 10.7MHz, the sampling frequency is 42.8MHz, the signal bandwidth is 200kHz, oversampling rate is 107, and one bit quantizer.

The summing amplifier and the quantizer form two of the most critical blocks in a continuous time delta sigma (CT ΔΣ) analog-to-digital converter (ADC). Most of the conventional CT ΔΣ ADC designs incorporate a voltage summing amplifier and a voltage-mode quantizer. The high gain-bandwidth (GBW) requirement of the voltage summing amplifier increases the overall power consumption of the CT ΔΣ ADC. In this work, a novel method of performing the operations of summing and quantization is proposed. A current-mode summing stage is proposed in the place of a voltage summing amplifier. The summed signal, which is available in current domain, is then quantized with a 3-bit current mode flash ADC. This current mode summing approach offers considerable power reduction of about 80% compared to conventional solutions [2]. The total static power consumption of the summing stage and the quantizer is 5.3mW. The circuits were designed in IBM 90nm process. The static and dynamic characteristics of the quantizer are analyzed. The impact of process and temperature variation and mismatch tolerance as well as the impact of jitter, in the presence of an out-of-band blocker signal, on the performance of the quantizer is also studied.