Software testing is a very time-consuming and tedious activity and accounts for over 25% of the cost of software development. In addition to its high cost, manual testing is unpopular and often inconsistently executed. Software Testing Environments (STEs) overcome the deficiencies of manual testing through automating the test process and integrating testing tools to support a wide range of test capabilities. Most prior work on testing is in single-thread applications. This thesis is a contribution to testing of distributed applications, which has not been well explored. To address two crucial issues in testing, when to stop testing and how good the software is after testing, a statistics-based integrated test environment which is an extension of the testing concept in Quality Programming for distributed applications is presented. It provides automatic support for test execution by the Test Driver, test development by the SMAD Tree Editor and the Test Data Generator, test failure analysis by the Test Results Validator and the Test Paths Tracer, test measurement by the Quality Analyst, test management by the Test Manager and test planning by the Modeller. These tools are integrated around a public, shared data model describing the data entities and relationships which are manipulable by these tools. It enables early entry of the test process into the life cycle due to the definition of the quality planning and message-flow routings in the modelling. After well-prepared modelling and requirements specification are undertaken, the test process and the software design and implementation can proceed concurrently. A simple banking application written using Java Remote Method Invocation (RMI) and Java DataBase Connectivity (JDBC) shows the testing process of fitting it into the integrated test environment. The concept of the automated test execution through mobile agents across multiple platforms is also illustrated on this 3-tier client/server application.

Data Plane Development Kit is a highly used library for creating network applications that can be run on all hardware. Data Plane Development Kit has a component called Service Cores, which allows the main applications to create services that will run independently. These services are manually mapped to specific CPU cores, and are scheduled in a round-robin method. Because of the manual mapping, and the scheduling, the different load for each service can impact the start time for each service. By having services not run when supposed to, the throughput will degrade. In this thesis, we investigate and try to solve the issue by implementing a basic load balancer into the Service Core component. Our results show that an basic load balancer, that will balance upon reaching a CPU upper threshold, will increase the throughput of services while decreasing the delay between each service run.

Today media centers are often cluttered with multiple devices each controlled by their own remote control. It is often hard and/or painful to manage and utilize these devices, especially for inexperienced users. Simstream wants to build an innovative smart-TV that as much as possible centralizes functions and controls.  Operating the system should be intuitive and simple, yet experienced users should have access to more advanced operations. This requires acquiring several inputs as well as integrating the communication devices that are necessary to control the attached external devices. Whenever possible, we want to efficiently process every input while minimizing latencies.  As a result, we want all the frequent operation to be as quick and lightweight as possible in order to provide a high quality user experience even under high system loads. This project takes advantage of the widespread availability of touchscreen mobile devices in order to provide an innovative means of control over the television, with remote control mobile applications running on an user’s familiar device. A remote controller will also be sold together with the television, and this remote controller will also have a touchscreen, and will propose the same capabilities as the remote control mobile applications. Finally, this platform will be open to third-party applications, and as a result this thesis project developed a software development kit which is designed to be easy and familiar enough for developers to adopt it and create applications with it. Applications will be developed together with an interface displayed on the remote controllers, in order to tailor the remote control interface to what is currently displayed on the television screen / Idag är mediecentrer ofta belamrade med många enheter som är kontrollerade av sina egna fjärrkontroller. Det är ofta svårt och / eller smärtsamt att använda dessa enheterna, särskilt för oerfarna användare. Simstream vill bygga en innovativ smart TV som centraliserar funktioner och kontroller så mycket som möjligt. Att använda systemet ska vara intuitivt och enkelt, men mer erfarna användare ska också ha tillgång till mer avancerade funktioner. Detta kräver att förvärva flera indata samt att integrera kommunikationsenheterna som är nödvändiga för att kontrollera de anslutna externa enheter. När det är möjligt vill vi behandla varje indata på ett effektivt sätt oh samtidigt minimera latenser. Det här betyder att en operation som utförs ofta skall vara så snabb och så lätt som möjligt, för att förbättra användarupplevelse även när systemet är hårt belastad. Detta projekt drar fördel av den vidsprädda tillgången till pekskärma mobila enheter för att tillföra användaren en innovativ kontroll över sin TV, direkt från sin bekanta enhet. Slutligen kommer denna plattformen att vara öppen för tredjepartsutvecklare, och som ett resultat har detta examensarbete utvecklat ett software development kit som är gjort för att vara enkelt och välbekant nog för att utvecklare ska kunna använda det och skapa applikationer med det.

Web services provide organizations with a powerful infrastructure by which information and products may be distributed, but the task of supporting Web service systems can be difficult due to the complex nature of environment configuration and operation. Tools are needed to monitor and analyze such Enterprise environments so that appropriate engineering, quality control, or business activities can be pursued. This investigation resulted in the development of a software development kit, the WSLogA Framework, which is inspired by the vision of Cruz et al. (2003, 2004). The WSLogA Framework provides distributed Enterprise systems with a platform for comprehensive information capture and environment management. Five component groups are intended for employment to enable integrated workflows addressing monitoring and response activities, but these components may also be used individually to facilitate the phased integration of the WSLogA Framework into existing environments. The WSLogA Framework's design is portable across technology platforms (e.g., Java and .NET) and a variety of technologies may be substituted for the provided implementations to address unique system architectures. The WSLogA Framework supersedes existing logging and monitoring solutions in terms of both capability and intent. Applications based on the WSLogA Framework have an internal, real-time view of their operation and may adjust their environment based on the information provided by events related to their or system activities. The WSLogA Framework is intended as a software development kit around which system functionality may be organized and implemented, which makes the WSLogA Framework an architectural peer or complement to traditional application frameworks such as Spring's Web module. WSLogA Framework based systems should be envisioned as information appliance elements rather than traditionally scoped applications or services.

The interactive nature of web applications or “web apps” makes it an excellent medium for conveying complex scientific concepts to lay audiences and creating decision support tools that harness cutting edge modeling techniques. However, the technical expertise required to develop them represents a barrier for would-be developers. The barrier can be characterized by the following hurdles that developers must overcome: (1) identify, select, and install software that meet the spatial and computational capabilities commonly required for water resources modeling; (2) orchestrate the use of multiple FOSS and FOSS4G projects and navigate their differing application programming interfaces (APIs); (3) learn the multi-language programming skills required for modern web development; and (4) develop a web-safe and fully featured web site to host the app. This research has resulted in two primary products that effectively lower the barrier to water resources web app development: (1) a literature review of free and open source software (i.e. software review) and (2) Tethys Platform. The software review included earth science web apps that were published in the peer-reviewed literature in the last decade and it was performed to determine which FOSS4G and FOSS web software has been used to develop such web apps. The review highlights 11 FOSS4G software projects and 9 FOSS projects for web development that were used to develop 45 earth sciences web apps, which constitutes a significantly reduced list of possible software projects that could be used to meet the needs of water resources web app development—greatly lowering the barrier for entry to water resources web development. While the software review addresses the hurdle of identifying FOSS software to provide a web framework and spatial data capabilities for water resources web apps, there are still other hurdles that needed to be overcome to make development more viable. Tethys Platform was developed to address these other hurdles and streamline the development of water resources web apps. It includes (1) a suite of free and open source software that address the unique data and computational needs common to water resources web app development, (2) a Python software development kit for incorporating the functionality of each software element into web apps and streamlining their development, and (3) a customizable web portal that is used to deploy the completed web apps. Tethys Platform has been used to develop a broad array of web apps for water resources modeling and decision support.

<p>Communication and digital signal processing applications of today are often developed as fully integrated systems on one single chip and are implemented as application specific integrated circuits using e.g. VLSI technology. As the systems are getting more and more complex in terms of speed and performance the chip size and the design time tend to increase rapidly. This will result in search for cheaper and less time consuming alternatives. One alternative is field programmable gate arrays, so called FPGAs. The FPGAs are getting faster, cheaper and the number of gates increases all the time. A long list of ready to use functional blocks so called intellectual property (IP) blocks can be used in FPGAs. The latest FPGAs can also be bought with one or more embedded processors, in form of hard processor cores or as licenses for soft processor cores. This will speed up the design phase and of course also decrease the crucial time to market even more. </p><p>The purpose of this master’s thesis was to develop a waveform generator to generate a sine signal and a cosine signal, I and Q, used for radio/radar applications. The digital signals should have an output data rate of at least 100 MHz. The digital part of the system should be implemented in hardware using e.g. an FPGA. To convert the digital signals to analog signals two D/A converters are used. The analog signals, I and Q, should have a bandwidth of 1 MHz - 11 MHz. </p><p>The waveform generator was developed and implemented using a Virtex II FPGA from Xilinx. An embedded microprocessor within the FPGA, MicroBlaze, in form of a soft processor core was used to control the system. A user interface program running on the microprocessor was also developed. Testing of the whole system, both hardware and software, was done. The system is able to generate digital sine and cosine curves of an output data rate of 100 MHz.</p>

Communication and digital signal processing applications of today are often developed as fully integrated systems on one single chip and are implemented as application specific integrated circuits using e.g. VLSI technology. As the systems are getting more and more complex in terms of speed and performance the chip size and the design time tend to increase rapidly. This will result in search for cheaper and less time consuming alternatives. One alternative is field programmable gate arrays, so called FPGAs. The FPGAs are getting faster, cheaper and the number of gates increases all the time. A long list of ready to use functional blocks so called intellectual property (IP) blocks can be used in FPGAs. The latest FPGAs can also be bought with one or more embedded processors, in form of hard processor cores or as licenses for soft processor cores. This will speed up the design phase and of course also decrease the crucial time to market even more. The purpose of this master’s thesis was to develop a waveform generator to generate a sine signal and a cosine signal, I and Q, used for radio/radar applications. The digital signals should have an output data rate of at least 100 MHz. The digital part of the system should be implemented in hardware using e.g. an FPGA. To convert the digital signals to analog signals two D/A converters are used. The analog signals, I and Q, should have a bandwidth of 1 MHz - 11 MHz. The waveform generator was developed and implemented using a Virtex II FPGA from Xilinx. An embedded microprocessor within the FPGA, MicroBlaze, in form of a soft processor core was used to control the system. A user interface program running on the microprocessor was also developed. Testing of the whole system, both hardware and software, was done. The system is able to generate digital sine and cosine curves of an output data rate of 100 MHz.

Master thesis is dealing with issues and problems of packet queue management in high speed packet networks. Design implementation is made in VHDL hardware description language. In theoretical part of thesis are explained different types of mechanism used for providing quality of service in communication networks. Furthermore the brief description o VHDL, FPGA and framework Netcope Development Kit is a piece of theoretical part as well. The outcome of practical part contains a design, limiting packet queues based on Tocken Bucket mechanism. Design verification was made by simulations, synthesis and real implementation on smart NIC NFB-200G2QL. All kind of verificaion results are summerized in last three chapters.

This thesis describes the design of construction of the converter USB joystick on the Ethernet interface. In the first part are theoretically analyzed both protocols used for the converter. An analysis of current microprocessor trade and their possible using for application in this project. Next part including the specification of used microprocessor and all options of programming and debugging of the microprocessor. Another part deals with the detailed design of the hardware interface. The last part describes the software equipment of microprocessor and the final appreaciation of work.

Key-Value Stores (KVSs) are a type of non-relational databases whose data is represented as a key-value pair and are often used to represent cache and session data storage. Among them, Memcached is one of the most popular ones, as it is widely used in various Internet services such as social networks and streaming platforms. Given the continuous and increasingly rapid growth of networked devices that use these services, the commodity hardware on which the databases are based must process packets faster to meet the needs of the market. However, in recent years, the performance improvements characterising the new hardware has become thinner and thinner. From here, as the purchase of new products is no longer synonymous with significant performance improvements, companies need to exploit the full potential of the hardware already in their possession, consequently postponing the purchase of more recent hardware. One of the latest ideas for increasing the performance of commodity hardware is the use of slice-aware memory management. This technique exploits the Last Level of Cache (LLC) by making sure that the individual cores take data from memory locations that are mapped to their respective cache portions (i.e., LLC slices). This thesis focuses on the realisation of a KVS prototype—based on Intel Haswell micro-architecture—built on top of the Data Plane Development Kit (DPDK), and to which the principles of slice-aware memory management are applied. To test its performance, given the non-existence of a DPDKbased traffic generator that supports the Memcached protocol, an additional prototype of a traffic generator that supports these features has also been developed. The performances were measured using two distinct machines: one for the traffic generator and one for the KVS. First, the “regular” KVS prototype was tested, then, to see the actual benefits, the slice-aware one. Both KVS prototypeswere subjected to two types of traffic: (i) uniformtraffic where the keys are always different from each other, and (ii) skewed traffic, where keys are repeated and some keys are more likely to be repeated than others. The experiments show that, in real-world scenario (i.e., characterised by skewed key distributions), the employment of a slice-aware memory management technique in a KVS can slightly improve the end-to-end latency (i.e.,~2%). Additionally, such technique highly impacts the look-up time required by the CPU to find the key and the corresponding value in the database, decreasing the mean time by ~22.5%, and improving the 99th percentile by ~62.7%. / Key-Value Stores (KVSs) är en typ av icke-relationsdatabaser vars data representeras som ett nyckel-värdepar och används ofta för att representera lagring av cache och session. Bland dem är Memcached en av de mest populära, eftersom den används ofta i olika internettjänster som sociala nätverk och strömmande plattformar. Med tanke på den kontinuerliga och allt snabbare tillväxten av nätverksenheter som använder dessa tjänster måste den råvaruhårdvara som databaserna bygger på bearbeta paket snabbare för att möta marknadens behov. Under de senaste åren har dock prestandaförbättringarna som kännetecknar den nya hårdvaran blivit tunnare och tunnare. Härifrån, eftersom inköp av nya produkter inte längre är synonymt med betydande prestandaförbättringar, måste företagen utnyttja den fulla potentialen för hårdvaran som redan finns i deras besittning, vilket skjuter upp köpet av nyare hårdvara. En av de senaste idéerna för att öka prestanda för råvaruhårdvara är användningen av skivmedveten minneshantering. Denna teknik utnyttjar den Sista Nivån av Cache (SNC) genom att se till att de enskilda kärnorna tar data från minnesplatser som är mappade till deras respektive cachepartier (dvs. SNCskivor). Denna avhandling fokuserar på förverkligandet av en KVS-prototyp— baserad på Intel Haswell mikroarkitektur—byggd ovanpå Data Plane Development Kit (DPDK), och på vilken principerna för skivmedveten minneshantering tillämpas. För att testa dess prestanda, med tanke på att det inte finns en DPDK-baserad trafikgenerator som stöder Memcachedprotokollet, har en ytterligare prototyp av en trafikgenerator som stöder dessa funktioner också utvecklats. Föreställningarna mättes med två olika maskiner: en för trafikgeneratorn och en för KVS. Först testades den “vanliga” KVSprototypen, för att se de faktiska fördelarna, den skivmedvetna. Båda KVSprototyperna utsattes för två typer av trafik: (i) enhetlig trafik där nycklarna alltid skiljer sig från varandra och (ii) sned trafik, där nycklar upprepas och vissa nycklar är mer benägna att upprepas än andra. Experimenten visar att i verkliga scenarier (dvs. kännetecknas av snedställda nyckelfördelningar) kan användningen av en skivmedveten minneshanteringsteknik i en KVS förbättra förbättringen från slut till slut (dvs. ~2%). Dessutom påverkar sådan teknik i hög grad uppslagstiden som krävs av CPU: n för att hitta nyckeln och motsvarande värde i databasen, vilket minskar medeltiden med ~22, 5% och förbättrar 99th percentilen med ~62, 7%.