The thesis is focused on designing OFDM modem, which should be implemented into the FPGA device. The advantages of using OFDM signals in order to provide high baud rates together with high multipath immunity has provoked a mass expansion into media systems such as DSL, DVB, Wi-Fi, WLAN, etc. . Thanks to this technology we can quarantee high modulation rates with minimal negative disturbance eects. The rst part is dedicated to characterise OFDM signals, their generation and the algorithm producing the OFDM which is implemented in DSP devices. For the purpose of using the fastest algorithm, the Fast Fourier Transform using Cooley-Tukey algorithm was shown. Before we can implement OFDM modem into the FPGA device, we have to simulate its correct function. Because there is no OFDM analyser available at our departement, its necessary to prove its correct function by simulations. Therefore a large part of this thesis is focused on simulations using Matlab and ModelSim, in order to show comparison between the theoretical, and simulated results. Between the theoretical and practical simulations there is a part which shows the brief characteristics of available FPGA devices. Detailed view is presented just for the Virtex II device, which the implementation is made for. As a suitable FPGA device, we have chosen Virtex II XC2V1000 which is available for students. In the last part the measured results were shown to prove the corect function of the modem. Programming the FPGA using VHDL language is realized in the software ISE Xilinx (distributed in Xilinx software support). All programmed scrits and data used in this thesis are included on distributed media.

This master's thesis dissertates of partial reconfiguration methods based on programmable structures. In theoretical part it deals with difference and modular-based method of Xilinx's FPGAs Partial reconfiguration. Options of both reconfiguration techniques were written for Spartan 3, Virtex II, Virtex 4 and Virtex 5 processors. Diference-based method was in practical part tested on Spartan 3E Starter Kit and modular-based on ML501 board. All configuration bitstreams are included on CD. Xilinx Inc. provided all needed software tools such as ISE9.2i and PlanAHEAD.

Thèse numérisée par la Division de la gestion de documents et des archives de l'Université de Montréal.

Thèse numérisée par la Division de la gestion de documents et des archives de l'Université de Montréal

There is currently a strong trend towards embedding Internet capabilities into electronics and everyday appliances. Most network controllers used in small appliances or for specialized purposes are built using micro controllers. However there are many applications where a hardware-oriented approach using Application Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs) is more suitable. One of the features of FPGAs that cannot be integrated into ASICs is runtime reconfiguration in which, certain portions of the chip are reconfigured at runtime while the other parts continue to operate normally. This feature is required for network controllers with multiple data transfer channels that need to preserve the state of the static channels while reconfiguration is taking place. It is also required for controllers with space constraints in terms of FPGA resources or time constraints in terms of reconfiguration times. This thesis explores the impact of partial reconfiguration on the performance of a network controller. An FPGA-based network controller that supports partial reconfiguration has been designed and constructed. Partial bitstreams that can configure certain channels of the network controller without a ecting the functioning of others have been created. Experiments have been performed that quantify the manner in which, the performance of the controller can be changed by loading these partial bitstreams onto the FPGA. These experiments demonstrated the advantages of using partial reconfiguration to change network-related parameters at runtime to optimize performance of the network controller. / Master of Science

FPGA implementation tools have not kept pace with growing FPGA density. It is common for non-trivial designs to take multiple hours to go through the entire FPGA toolflow (synthesis, mapping, placement, routing, bitstream generation). FPGA implementation tool runtime is a major hindrance to FPGA Productivity. In modern FPGA designs, designers often change logic and/or connections in an already existing design. If small modifications are made to a particular module in a design, then almost the entire design will go through most of the FPGA toolflow again. This can be time consuming for complex designs and hinder productivity of FPGA designers. The main goal of this thesis is to improve FPGA productivity by reducing FPGA design implementation time for modifications made to an already existing design for rapid system deployment. In this thesis, a toolkit is presented, which is capable of making design modifications at a lower level of abstraction for already existing designs on Xilinx FPGAs. The toolkit is a part of the open-source RapidSmith framework and includes the EDIF parser, mapper, placer, and router. It can be used to change logic and/or modify connections. Modules can be placed, unplaced, relocated, and/or duplicated with ease using this toolkit. Significant time-savings were seen by making use of the toolkit along-with the standard Xilinx FPGA toolflow, for making design modifications to already existing designs. / Master of Science

As technology evolves and new methods for designing radios arise, it becomes necessary to continue the search for fast and flexible development environments. Some of these new technologies include software defined radio (SDR), Field Programmable Gate Arrays (FPGAs), and the open source project GNU Radio. Software defined radio is a concept that GNU Radio has harnessed to allow developers to quickly create flexible radio designs. In terms of hardware, the maturity of FPGAs give radio designers new opportunities to develop high-speed radios having high-throughput and low-latency, yet the conventional build-time for FPGAs is a limiting factor for productivity. Recent research has lead to reductions in build-time by using FPGAs in a non-traditional manner, meaning productivity no longer has to be sacrificed. The AgileHW project demonstrated this concept and will be used as a basis to develop an overlaying architecture that uses a combination of the technologies mentioned to create a flexible, open, and efficient environment for radio development. This thesis discusses the realization of this architecture with the use of Xilinx FPGAs as a hardware accelerator for an enhanced GNU Radio. / Master of Science

Modern FPGAs contain routing resources easily exceeding millions of wires. While mainstream design flows and place-and-route tools make very good use of these routing resources, they do so at the cost of very significant processing time. A well established alternative scheme is to modify or generate configuration bitstreams directly, resulting in more dynamic designs and shorter processing times. This thesis introduces a complete set of alternate wire databases for Xilinx Virtex, Virtex-E, and Virtex-II FPGAs, suitable for standalone use or as an addition to the JBits API. The databases can be used to route or trace through any device in these families, and can generate the necessary bitstream configurations with the help of JBits or an independent bitstream interface. / Master of Science

As hardware applications become increasingly complex, the supporting technology needs to evolve and adapt to the demands. Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit, General Purpose Processor, and System on Chip are the preferred devices for solving computational problems. Each of these platforms has its own specific advantages and disadvantages, which need to be accounted for during application development. Flexible radio communications has been dominated by Software Defined Radios. However, research in industry and universities has successfully developed run-time reconfiguration tools to make FPGA designs more flexible and thus vastly reducing configuration times. Developers now have a more powerful platform with dense Digital Signal Processor resources and the flexibility of SDR. Xilinx offers tools such as partial reconfiguration, which is a special modification of the standard tool-flow that supports configuration of the selected partial regions on an FPGA. The AgileHW project improves on the Xilinx tools resource allocation and routing scheme to increase the design agility and productivity. This thesis advances the AgileHW reconfigurable platform so developers can use the newer technology to build enhanced designs. / Master of Science

Nos últimos anos, houve um grande avanço na computação reconfigurável, em particular em hardware que emprega Field-Programmable Gate Arrays. Porém, esse aumento de capacidade e desempenho aumentou a distância entre a capacidade de projeto e a disponibilidade de tecnologia para o desenvolvimento do projeto. As linguagens de programação imperativas de alto nível, como C, são mais apropriadas para o desenvolvimento de aplicativos complexos que as linguagens de descrição de hardware. Por isso, surgiram diversas ferramentas para o desenvolvimento de hardware a partir de código em C. A ferramenta ChipCflow, da qual faz parte este projeto, é uma delas. A execução dos programas por meio dessa ferramenta será completamente baseada em seu fluxo de dados, seguindo o modelo dinâmico encontrado nas arquiteturas de computadores a fluxo de dados, aproveitando ao máximo o paralelismo considerado natural desse modelo e as características do hardware parcialmente reconfigurável. Neste projeto em particular, o objetivo é a prova de conceito (proof of concept) para a criação de instâncias, em forma de operadores, de um algoritmo ChipCflow em hardware parcialmente reconfigurável, tendo como base a plataforma Virtex da Xilinx / In recent years, reconfigurable computing has become increasingly more advanced, especially in hardware that uses Field-Programmable Gate Arrays. However, the increase of performance in FPGAs accumulated the gap between design capacity and technology for the development of the design. Imperative high-level programming languages such as C are more appropriate for the development of complex algorithms than hardware description languages (HDL). For this reason, many ANSI C-like programming tools for the development of hardware came to existence. The ChipCflow project, of which this project is part, is one of these tools. The execution of algorithms through this tool will be completely directed by data flow, according to the dynamic model found on Dataflow Architectures, taking advantage of its natural high levels of parallelism and the characteristics of the partially reconfigurable hardware. In this project, the objective is a proof of concept for the creation of instances, in the form of operators, of a ChipCflow algorithm on a partially reconfigurable hardware, taking as reference the Xilinx Virtex boards