Today, wireless communications is used more then ever before. Wired systems are replaced with wireless versions. New methods and transmission standards are developed and tested. The purpose of this thesis is development of a flexible high-performance System Test Platformfor test of the SoCTRix Wireless LAN Transceiver. The result is a Xilinx Virtex-II FPGA based System Test Platform board with CardBus PC Card interface to a computer. The hardware achieved has the following features: - 8-layer PCB - PCMCIA CardBus PC Card interface, enabling 133 MB/s data throughput - 1M Gate Virtex-II FPGA with reprogrammable configuration memory - Debugging via LEDs and Logic Analyzer connectors - 2x SPI EEPROM - 40 MHz system clock - Easy connection of two daughter-boards Specially designed for wireless transmitter development, can also be used for other computer related highperformance applications.

Digital Radio Frequency Memory (DRFM) is a technique widely used by the defense industry in, for example, electronic countermeasure equipment for generating false radar targets. The purpose of the DRFM technique is to use high-speed sampling to digitally store and recreate radio frequency and microwave signals. At Saab Bofors Dynamics AB the technique is used, among others, in the Electronic Warfare Simulator (ELSI). The DRFM technique is implemented in a full-custom ASIC circuit that has been mounted on circuit boards in ELSI. Today, the progress in the programmable hardware field has made it possible to implement the DRFM design in a Field Programmable Gate Array (FPGA). The FPGA technology has many advantages over a full custom ASIC design. Hence, the purpose of this master's thesis has been to develop a new DRFM design that can be implemented in an FPGA, using a hardware description language called VHDL. The method for this master's thesis has been to first establish a time plan and a requirement specification. After that, a design specification has been worked out based on the requirement specification. The two specifications have served as a basis for the development of the DRFM circuit. One of the requirements on the design was that the circuit should be able to communicate through an external Ethernet interface. A part of the work has, thus, been to review available external Ethernet modules on the market. The result is a DRFM design that has been tested through simulations. The tests shows that the design works as described in the design specification.

Τα ενσωματωμένα υπολογιστικά συστήματα έχουν αρχίσει να χρησιμοποιούνται ολοένα και περισσότερο τα τελευταία χρόνια, όχι μόνο σε βιομηχανικές ή άλλες εξεζητημένες εφαρμογές αλλά και στην καθημερινότητα μας. Αυτό οφείλεται στο γεγονός ότι η συγκεκριμένη τεχνολογία είναι φτηνότερη, ευέλικτη και λιγότερο ενεργοβόρος σε σχέση με τα αντίστοιχα ηλεκτρονικά κυκλώματα που χρησιμοποιούνταν παλιότερα. Η παρούσα διπλωματική εργασία περιγράφει αναλυτικά τη διαδικασία για τη σωστή ρύθμιση του συστήματος μας και την μεταγλώττιση (compilation) του πυρήνα του Linux προκειμένου να τρέχει χωρίς προβλήματα πάνω στην FPGA πλακέτα της Xilinx, Virtex 5. Σαν επεξεργαστή επιλέξαμε να χρησιμοποιήσουμε τον soft - core επεξεργαστή της Xilinx microblaze,προσθέτοντας σαν επιπλέον περιφερειακά την οθόνη TFT καθώς και την θύρα PS/2. Στη συνέχεια προκειμένου να καταδείξουμε τις δυνατότητες που έχει το σύστημα που “χτίσαμε”, εγκαταστήσαμε γραφικό περιβάλλον με ορισμένες εφαρμογές και εκτελούμε κρυπτογραφικές συναρτήσεις από το terminal του λειτουργικού μας. / The embedded computer systems have recently started to be present in a number of implementations, not only in the industrial setting but also in normal life applications. This is due to the fact that this particular technology is cheaper, more efficient and less power - consuming than its dedicated electronic counterparts. In this diploma thesis we will study the process for the proper configuration of our system and the compilation of Linux Kernel in order to have a completely functional embedded system on the Xilinx' s FPGA board, Virtex 5. We used the Microblaze soft - core processor and we added the TFT monitor and the PS/2 port as extra components to our system. Furthermore in order to present the capabilities of our system, we added the Nano - X graphical user interface and we run cryptographic algorithms through the terminal of the operating system.

Test Tools are very important in the design of a system. They generally simulate a working environment, only at a higher speed, or with less frequently occurring test cases. In the verification of protocols based on the Fibre Channel physical layer, this becomes a necessity, as errors can be non-existent or very unusual in normal operating environments. Most systems need to be able to handle these unexpected events nonetheless. Therefore, there is a need for a method of introducing these errors in a controlled way. A bit error generation and logging tool for two proprietary protocols based on the Fibre Channel physical layer has been developed. The hardware platform consists mainly of a Virtex II Pro FPGA with accompanying I/O support. Control of the hardware is handled by a graphical user interface residing on a PC. Communication between the hardware and the PC is handled with a UART. The final implementation can handle four parallel one way links, or two full duplex links, independently. This report describes the implementation and the necessary theoretical background for this.

Nowadays, FPGAs are large enough to host entire system-on-chip designs, wherein a soft core processor is often an integral part. High performance of the processor is always desirable, so there is an interest in finding faster solutions.This report aims to describe the work and results performed by Karl Bengtson and Olof Andersson at ISY. The task was to continue the development of a soft core microprocessor, originally created by Andreas Ehliar. The first step was to decide a more widely adopted instruction set for the processor. The choice fell upon the MIPS32 instruction set. The main work of the project has been focused on implementing support for MIPS32, allowing the processor to execute MIPS assembly language programs. The development has been done with speed optimization in mind. For every new function, the effects on the maximum frequency has been considered, and solutions not satisfying the speed requirements has been abandoned or revised.The performance has been measured by running a benchmark program—Coremark. Comparison has also been made to the main competitors among soft core processors. The results were positive, and reported a higher Coremark score than the other processors inthe study. The processor described herein still lacks many essential features. Nevertheless, the conclusion is that it may be possible to create a competitive alternative to established soft processors. / FPGAer används idag ofta för stora inbyggda system, i vilka en mjuk processor ofta spelar en viktig roll. Hög prestanda hos processorn är alltid önskvärt, så det finns ett intresse i att hitta snabbare lösningar. Denna rapport skall beskriva det arbete och de resultat som uppnåtts av Karl Bengtson och Olof Andersson på ISY. Uppgiften var att fortsätta utvecklandet av en mjuk processor, som ursprungligen skapats av Andreas Ehliar. Första steget var att välja ut en mer allmänt använd instruktionsuppsättning för processorn. Valet föll på instruktionsuppsättningsarkitekturen MIPS32. Projektets huvutarbete har varit fokuserat på att implementera stöd för MIPS32, vilket ger processorn möjlighet att köra assemblerprogram för MIPS.Utvecklingen har gjorts med hastighetsoptimering i beaktning. För varje ny funktion har dess effekter på maxfrekvensen undersökts,och lösningar som inte uppfyllt hastighetskraven har förkastats eller reviderats. Prestandan har mätts med programmet Coremark. Det har också gjorts jämförelser med huvudkonkurrenterna bland mjuka processorer. Resultaten var positiva, och rapporterade ett högre Coremarkpoäng än de andra processorerna i studien. Slutsatsen är att det ärmöjligt att skapa ett alternativ till de etablerade mjuka processorerna, men att denna processor fortfarande saknar väsentliga funktioner som behövs för att utgöra en mogen produkt.

The aim of this thesis was to design and implement PCI Express Bridge. The main purpose of this unit is to help application engineers who develop various FPGA based accelerators. The implemented unit transforms complex PCI Express based system bus interface to more common and scalable interface of internal bus for on-chip components interconnection. This allows engineers to focus on the development of their target applications, not on a complicated communication protocol. The unit was implemented in the VHDL language, synthesized for Virtex-5 based FPGAs as well as completely tested on ML555 and COMBOv2 cards. The acquired results show that the component reaches the throughput of 7 Gb/s, which is the theoretical limitation of underlying protocols.

The field-programmable gate array (FPGA) is a dynamically reconfigurable digital logic chip used to implement custom hardware. The large densities of modern FPGAs and the capability of the on-thely reconfiguration has made the FPGA a viable alternative to fixed logic hardware chips such as the ASIC. In high-performance computing, FPGAs are used as co-processors to speed up computationally intensive processes or as autonomous systems that realize a complete hardware application. However, due to the limited capacity of FPGA logic resources, denser FPGAs must be purchased if more logic resources are required to realize all the functions of a complex application. Alternatively, partial reconfiguration (PR) can be used to swap, on demand, idle components of the application with active components. This research uses PR to swap components to improve the performance of the application given the limited logic resources available with smaller but economical FPGAs. The swap is called ”resource sharing PR”. In a pipelined design of multiple hardware modules (pipeline stages), resource sharing PR is a technique that uses PR to improve the performance of pipeline bottlenecks. This is done by reconfiguring other pipeline stages, typically those that are idle waiting for data from a bottleneck, into an additional parallel bottleneck module. The target pipeline of this research is a two-stage “slow-toast” pipeline where the flow of data traversing the pipeline transitions from a relatively slow, bottleneck stage to a fast stage. A two stage pipeline that combines FPGA-based hardware implementations of well-known Bioinformatics search algorithms, the X! Tandem algorithm and the Smith-Waterman algorithm, is implemented for this research; the implemented pipeline demonstrates that characteristics of these algorithm. The experimental results show that, in a database of unknown peptide spectra, when matching spectra with 388 peaks or greater, performing resource sharing PR to instantiate a parallel X! Tandem module is worth the cost for PR. In addition, from timings gathered during experiments, a general formula was derived for determining the value of performing PR upon a fast module.

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