<p> The melt equilibria of the system CaF2-CaMgSi2O6 has been studied at atmospheric pressure by using a modified quenching method. This system is characterized by a simple binary eutectic at CaF2 43.4, CaMgSi2O6 56.5 weight percent at 1082t 2°C; neither solid solution nor intermediate compound was found. Some special features have been discussed in detail. The results of the study of the system CaF2-CaMgSi2O6, together with suppositions regarding the system CaF2-CaMgSi2O6-CaCO3, have tentatively been applied to a hypothesis regarding the origin of certain skarns which are considered to be formed by differential melting of impure limestone in regional metamorphic terrains. The applications of this binary system to the theoretical chemistry of Portland cement burning is also incidentally considered. </p> / Thesis / Master of Science (MSc)

Industrial programs written on Programmable Logic Controllers (PLCs) have become an essential component of many modern industries, including automotive, aerospace, manufacturing, infrastructure, and even amusement parks. As these safety-critical systems become larger and more complex, ensuring their continuous error-free operation has become a significant and important challenge. Formal methods are a potential solution to this issue but have traditionally required substantial time and expertise to deploy. This usability issue is compounded by the fact that PLCs are highly proprietary and have substantial licensing costs, making it difficult to learn about or deploy formal methods on them. This thesis presents the OPPP (Open-source Proving of PLC Programs) system as a solution to this usability issue. The OPPP system allows the end-to-end creation and verification of PLC programs from within the development environment. The system is created with an emphasis on being easy to use, with formal constraints presented in English phrases that require no special knowledge to understand. The system uses entirely open-source components, including modified versions of both the OpenPLC development environment and the PLCverif verification platform. The OPPP system is then demonstrated to formalize the requirements of two college-level introductory PLC programming problems. It is further demonstrated to correctly find errors in and verify the correctness of a known good and known bad solution to each problem.

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While aspect-oriented programming (AOP) addresses the introduction of “aspects” at the code level, we argue that addressing this at the level of software architecture is conceptually and methodologically more adequate, since many aspects, that is, “crosscutting concerns”, are formulated already in the requirements, and therefore can be dealt with in a more controlled manner in the “earlier” phase of software architecture design. We use the precise concept of software architectures organised as diagrams over a category of component specifications, where the architecture semantics are defined as a colimit specification (Fiadeiro and Maibaum, 1992). The diagram structure suggests aspect introduction via an appropriate variant of graph transformation. Singlepushout rewriting in categories of total homomorphisms has already been used previously for different kinds of “enrichment” transformations; we identify “zigzag-path homomorphisms” as producing a category where many practically useful aspect introductions turn out to be such single-pushout transformations, and present the relevant theorems concerning pushout existence and pushout construction. Practical aspect introduction (e.g., privacy) always breaks some properties (e.g., “message can be read in transit”); therefore, aspect introduction transformations cannot be designed to be semantics preserving. Our special categorical setting enables selective reasoning about property preservation in the transformed specifications, and property introduction from the introduced aspects. This method enables us to detect and resolve both conflicts and undesirable emergent behaviors that arise from aspect introduction or interaction. We have developed tool support to introduce and analyze aspects at the system architecture level through zigzag graph transformation. The implementation is based on Hets, an initiative of Mossakowski et al. (2007) and consists of two key parts: the language development and the zigzag transformation. The development of the MFLogic language is based on the specification language Casl (Astesiano et al., 2002) and uses the logic introduced by Fiadeiro and Maibaum (1992). Besides parsing, syntactic and static semantics correctness checking, the language inclusion in Hets opens the door for automatic property preservation analysis and conflict detection. The main contribution of the tool support in Hets is the automatic aspect introduction and the “result architecture” generation by applying our zigzag graph transformation. / Thesis / Doctor of Philosophy (PhD)

Various theories have been proposed to describe vehicular traffic flow in cities on an aggregate level. This dissertation work shows that a number of MFDs exist in an urban network. The number of MFDs basically indicate the existence of different levels of service on different network routes. It also demonstrate that the modification of control strategy can optimize the signal timing plan for the links with high congestion and spillbacks. With the proposed control strategy, the location of points are shifted from lower MFDs to upper MFDs which means the congestion are reduced and the overall network traffic flow operation is improved. In this thesis, the emergency vehicle preemption (EVP) operation is also evaluated by using the MFDs. The concept of MFD can help to illustrate the effect on various types of roads due to EVP operation. The results show that the volume of links along the emergency route is increased and the volume of other links closed to the emergency route is decreased due to preemption. The researchers and practitioners can apply the proposed approach to identify the affected links and minimize the total network delay during EVP. / Master of Science

Unified Modeling Language (UML) is recognized as a de facto standard for modeling various typesof systems. However, its lack of formal semantics hinders the ability to perform formal verification, which is crucial to ensure the correctness of the models throughout the modeling process. Rebeca isan actor-based modeling language designed to formally verify reactive concurrent systems. Previous work has attempted to bridge the gap and provide a translation to take advantage of both UML and Rebeca’s benefits. These methods either require multiple UML diagrams and an understanding of Rebeca, or lack implementation solutions. We conducted experiments to explore the potential of zero-shot and few-shot learning with ChatGPT-4 as a tool for automating the translation from UML state diagrams to Rebeca code. The results indicated that the translation from UML state diagrams to Rebeca code can be partially made and they are not sufficient to derive correct Rebeca models. To mitigate this, we augment state diagrams with metadata, which resulted in the generated code having minor errors and requiring slight adjustments to be able to be compiled in the Rebeca model checking tool, Afra. The conclusion is that ChatGPT-4 can potentially facilitate the process of transforming UML state diagrams into executable Rebeca code with minimal additional information. We provide a translation procedure of Rebeca code to UML state diagrams, a conceptual mapping of them in reverse, and a dataset that can be used for further research. The dataset and the results are published in the GitHub repositoryof our project

As the number of transistors per unit chip area increases, the power dissipation of the chip becomes a bottleneck. New nano-technology materials have been proposed as viable alternatives to CMOS to tackle area and power issues. The power consumption can be minimized by the use of reversible logic instead of conventional combinational circuits. Theoretically, reversible circuits do not consume any power (or consume minimal power) when performing computations. This is achieved by avoiding information loss across the circuit. However, use of reversible circuits to implement digital logic requires development of new Electronic Design Automation techniques. Several approaches have been proposed and each method has its own pros and cons. This often results in multiple designs for the same function. Consequently, this demands research in efficient equivalence checking techniques for reversible circuits. This thesis explores the optimization and equivalence checking of reversible circuits. Most of the existing synthesis techniques work in two steps — generate an original, often sub-optimal, implementation for the circuit followed optimization of this design. This work proposes the use of Binary Decision Diagrams for optimization of reversible circuits. The proposed technique identifies repeated gate (trivial) as well as non-contiguous redundancies in a reversible circuit. Construction of a BDD for a sub-circuit (obtained by sliding a window of fixed size over the circuit) identifies redundant gates based upon the redundant variables in the BDD. This method was unsuccessful in identifying any additional redundancies in benchmark circuits; however, hidden non-contiguous redundancies were consistently identified for a family of randomly generated reversible circuits. As of now, several research groups focus upon efficient synthesis of reversible circuits. However, little work has been done in identification of redundant gates in existing designs and the proposed peephole optimization method stands among the few known techniques. This method fails to identify redundancies in a few cases indicating the complexity of the problem and the need for further research in this area. Even for simple logical functions, multiple circuit representations exist which exhibit a large variation in the total number of gates and circuit structure. It may be advantageous to have multiple implementations to provide flexibility in choice of implementation process but it is necessary to validate the functional equivalence of each such design. Equivalence checking for reversible circuits has been researched to some extent and a few pre-processing techniques have been proposed prior to this work. One such technique involves the use of Reversible Miter circuits followed by SAT-solvers to ascertain equivalence. The second half of this work focuses upon the application of the proposed reduction technique to Reversible Miter circuits as a pre-processing step to improve the efficiency of the subsequent SAT-based equivalence checking. / Master of Science