Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1982. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING / Bibliography: leaf 22. / by Inwhan Choi. / B.S.

Research was supported by the Energy Research and Development Administration as part of a contract with Arthur D. Little, inc.

Orientador: Rodolfo Jardim de Azevedo / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-10T11:21:32Z (GMT). No. of bitstreams: 1 Sigrist_ThiagoMassariolli_M.pdf: 1159366 bytes, checksum: 1b73082be801a7391d4d5176c6e49207 (MD5) Previous issue date: 2007 / Resumo: O surgimento dos SoCs (Systems-on-Chip) levou ao desenvolvimento das metodologias de projeto baseadas em TLM (Transaction-Level Modelling), que oferecem diversas etapas de modelagem intermediárias entre a especificação pura e a descrição sintetizável RTL (Register Transfer Level ), tornando mais tratável o projeto de sistemas dessa complexidade. Levando-se em consideração que esses sistemas geralmente possuem microprocessadores como módulos principais, torna-se desejável o uso de linguagens de descrição de arquiteturas (ADLs ? Architecture Description Languages) como ArchC e suas ferramentas para que seja possível modelar esses processadores e gerar módulos simuladores para eles em uma fração do tempo tradicionalmente gasto com essa tarefa. Porém, ArchC, em sua penúltima versão, a 1.6, possui utilidade limitada para esse fim, pois os simuladores que é capaz de gerar são autocontidos, não sendo facilmente integráveis aos modelos TLM em nível de sistema como um todo. Este trabalho consiste em uma remodelagem da linguagem ArchC e sua ferramenta acsim de modo a acrescentar essa capacidade de integração aos simuladores funcionais interpretados que é capaz de gerar, dando assim origem à versão 2.0 de ArchC / Abstract: The advent of SoCs (Systems-on-Chip) lead to the development of project methodologies based on TLM (Transaction-Level Modelling), which consist of several modelling layers between pure specifications and synthesizable RTL (Register Transfer Level ) descriptions, making the complexity of such systems more manageable. Considering that those systems usually have microprocessors as main modules, it is desirable to use architecture description languages (ADLs) like ArchC and its toolkit to model those processors and generate simulator modules for them in a fraction of the time usually spent in that task. However, ArchC, in its previous version, 1.6, has limitations for that use, since the simulators it generates are self-contained, thus hard to integrate to TLM system-level models. This work consists in remodelling ArchC and its acsim tool, adding this ability of integration to its functional interpreted simulators, leading to version 2.0 of ArchC / Mestrado / Sistemas de Computação / Mestre em Ciência da Computação

Orientador: Rodolfo Jardim de Azevedo / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-22T19:27:44Z (GMT). No. of bitstreams: 1 Guedes_Marcelo_M.pdf: 3596190 bytes, checksum: cb76d95f3dd3a8542b2e08b6b38550e0 (MD5) Previous issue date: 2012 / Resumo: A dissertação apresenta acSynth, um conjunto de ferramentas integradas que tem por objetivo fornecer uma plataforma aberta de desenvolvimento e síntese de projetos a partir de descrições em ADL ArchC. Como primeiro trabalho, acSynth foi equipado com ferramentas para caracterização de consumo de energia de processadores através do método Tiwari. Isto foi concretizado através da composição das ferramentas PowerSC, acPower e acPowerGen, capacitando acSynth a obter e armazenar informações de consumo de energia. Estes dados podem, então, ser utilizados em simulações em acSim, com geração automática de relatórios em nível ADL. Após a caracterização, é possível distribuir as informações coletadas para evitar reexecutar o fluxo para as mesmas ferramentas e processadores. O trabalho apresenta resultados de caracterização dos processadores MIPS-I Plasma e SPARCv8 Leon3, bem como integração com as ferramentas de síntese da Altera e da Xilinx. Os processadores foram submetidos a testes com os benchmarks acStone, Mibench e Mediabench, com elaboração de relatórios de consumo de energia e gráficos de perfil energético no tempo. Um estudo do erro da caracterização foi apresentado. Para testes com MIPS-I o erro efetivo sobre plataforma Xilinx variou de 0,02% a 61,05%, com 91% dos casos com erro menor ou igual a 30%. Em plataforma Altera o erro efetivo variou de 0,01% a 17,49% com 96% dos casos com erro menor ou igual a 15%. Para testes com SPARCv8 em plataforma Xilinx o erro efetivo variou de 0,14% a 40,66% com 95% dos casos com erro menor ou igual a 20%. Adicionalmente, desenvolveu-se um processador MIPS-I pipelined através do fluxo da ferramenta acRTL. Um histórico do processo com detalhes dos prós e contras é apresentado. Um arquivo com dados de consumo de energia das instruções suportadas foi elaborado. Por fim, energia, área e desempenho foram estudados e comparados ao processador Plasma. As principais contribuições deste trabalho são: interconexão de ferramentas e mostra dos benefícios obtidos com isto; apresentação de uma abordagem de caracterização de consumo de energia de processadores no nível de arquitetura; demonstração de um método funcional para expansão de acSim para abarcar novos aspectos de simulação em alto nível; aplicação prática de acRTL / Abstract: This work presents acSynth, an integrated framework for development and synthesis based on ArchC ADL descriptions. In its first application, acSynth includes characterization tools to allow power consumption analysis for supported processor architectures, through Tiwari's method. The power analysis and characterization tools were achieved by integrating PowerSC, acPower and acPowerGen, allowing acSynth to gather, process and store power consumption data in order to create power reports. This data could then be used in acSim simulations, generating ADL level power analysis reports automatically. We show characterization results for MIPS-I Plasma processor and SPARCv8 Leon3 processor using two different synthesis tools and workflows, Altera and Xilinx. The processors were tested with acStone, Mibench and Mediabench benchmarks, generating power reports and energy consumption profile graphs with energy per time data. We analyzed the error comparing to RTL simulations. The analysis with MIPS-I and Xilinx tool set presented effective error between 0.02% and 61.05%, with 91% of the total number of analyzed cases presenting errors with less than or equal to 30%. Adopting Altera tool set, the effective error was between 0.01% and 17.49% with 96% of the total number of analyzed cases showing error with less than or equal to 15%. For SPARCv8 architecture, using Xilinx tool set, the effective error ranged between 0.14% and 40.66% with 95% of the total number of analyzed cases presenting errors with less than or equal to 20%. Furthermore, a MIPS-I pipelined processor was developed using the acRTL workflow. The complete development is detailed in this dissertation, highlighting the method advantages and disadvantages. The new processor power consumption data was collected and an acSynth power database generated. Finally, power, area and performance was investigated and compared to the stable processor Plasma. The main contributions of the present dissertation are: ArchC tool set integration showing the benefits in high level analysis; introduction of a new power characterization method in architecture level, expanding ArchC environment; design of a practical method to expand the acSim analysis and behavior, covering new high level simulation aspects; the practical use of acRTL / Mestrado / Ciência da Computação / Mestre em Ciência da Computação

A design and implementation of a multimodule chip-level simulator whose source description language is based on the original GSP2 system is described. To enhance the simulation speed, a special addressing ("sharing single memory location") scheme is used in the implementation of pin connections. The basic data structures and algorithms for the simulator are described. The developed simulator can simulate many digital devices interconnected as a digital network. It also has the capability of modeling external buses and handling the suspension of processes in the environment of multimodule simulation. An example of a multimodule digital system simulation is presented. / M.S.

A laboratory study was conducted to determine nitrogen removal rates from a land-applied wastewater as a function of the length of time the wastewater remained in the root zone. A digital simulation model was used as an aid in describing soil water (and wastewater) movement through the root zone under wet conditions (i.e. root zone 50- 75% saturated). A procedure was developed to predict the rate and volume of drainage as a function of initial soil moisture content, amount of liquid applied, and time after liquid application. An exact relationship between nitrogen removals and wastewater residence time in the root zone could not be developed. However, removals of up to 95% of applied NH₄-N were demonstrated in an 18-cm deep root zone with residence times as short as 2 hours. The exact nature of these removals was not determined. / Ph. D.

This work is a first step towards a long-term goal of understanding computations occurring in the brain and using those principles to make more efficient machines. The traditional computing paradigm calls for using digital supercomputers to simulate large scale brain-like neural networks resulting in large power consumption which limits scalability or model detail. For example, IBM's digital simulation of a cat brain with simplistic neurons and synapses consumes power equivalent to that of a thousand houses! Instead of digital methods, this work uses analog processing concepts to develop scalable, low-power silicon models of neurons which have been shown to be around ten thousand times more power efficient. This has been achieved by modeling the dynamical behavior of Hodgkin-Huxley (H-H) or Morris-Lecar type equations instead of modeling the exact equations themselves. In particular, the two silicon neuron designs described exhibit a Hopf and a saddle-node bifurcation. Conditions for the bifurcations allow the identification of correct biasing regimes for the neurons. Also, since the hardware neurons compute in real time, they can be used for dynamic clamp protocols in addition to computational experiments. To empower this analog implementation with the flexibility of a digital simulation, a family of field programmable analog array (FPAA) architectures have been developed in 0.35 um CMOS that provide reconfigurability in the network of neurons as well as tunability of individual neuron parameters. This programmability is obtained using floating-gate (FG) transistors. The neurons are organized in blocks called computational analog blocks (CAB) which are embedded in a programmable switch matrix. An unique feature of the architecture is that the switches, being FG elements, can be used also for computation leading to more than 50,000 analog parameters in 9 sq. mm. Several neural systems including central pattern generators and coincidence detectors are demonstrated. Also, a separate chip that is capable of implementing signal processing algorithms has been designed by modifying the CAB elements to include transconductors, multipliers etc. Several systems including an AM demodulator and a speech processor are presented. An important contribution of this work is developing an architecture for programming the FG elements over a wide dynamic range of currents. An adaptive logarithmic transimpedance amplifier is used for this purpose. This design provides a general solution for wide dynamic range current measurement with a low power dissipation and has been used in imaging chips too. A new generation of integrated circuits have also been designed that are 25 sq. mm in area and contain several new features including adaptive synapses and support for smart sensors. These designs and the previous ones should allow prototyping and rapid development of several neurally inspired systems and pave the path for the design of larger and more complex brain like adaptive neural networks.

Thesis (M.S.)--Mississippi State University. Department of Industrial Engineering. / Title from title screen. Includes bibliographical references.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2009. / Includes bibliographical references.

Thesis (M.S.)--State University of New York at Binghamton, Department of Systems Science and Industrial Engineering, 2009. / Includes bibliographical references (leaves: 150-155).