The resistor ladder (R/2R) digital-to-analogue converter (DAC) architecture is often used in high performance audio solutions due to its low-noise performance. Even high-end R/2R DACs suffer from static nonlinearity distortions. It was suspected that compensating for these nonlinearities would be possible. It was also suspected that this could improve audio quality in audio systems using R/2R DACs for digital-to-analogue (A/D) conversion. Through the use of models of the resistor ladder architecture a way of characterizing and measuring the faults in the R/2R DAC was created. A compensation algorithm was developed in order to compensate for the nonlinearities. The performance of the algorithm was simulated and an implementation of it was evaluated using an audio evaluation instrument. The results presented show that it is possible to increase linearity in R/2R DACs by compensating for static nonlinearity distortions. The increase in linearity can be quite significant and audible for the trained ear.

Presented thesis deals with the conceptual design of an integrated 11-bit, dual, bipolar, DA converter with current output. Converter is designed in I3T50E proprietary technology of ONSemiconductor. The converter is of a segmented architecture with 6 MSB bits unary and 4 LSB bits binary weighted. Work also describes basic general properties of DA converters, topology examples with regard to the project assignment. The design is assumed for automotive industrial field of application. The operating temperature range is from -40 Deg.C. up to 175 Deg.C. The qualities of produced integrated converter are measured and results are discussed.

This research looks into the design of an integrated in-phase/quadrature (I/Q) VCO operating at 5 GHz. The goal is to design a phase shifter that is implemented at the LO used for RF up conversion. The target application for the phase shifter is towards phased array antennas operating at 5 GHz. Instead of designing multiple VCOs that each deliver a variety of phases, two identical LC-VCOs are coupled together to oscillate at the same frequency and deliver four outputs that are 90 ° out of phase. By varying the amplitudes of the in-phase and quadrature signals independently using VGAs before adding them together, a resultant out-of-phase signal is obtained. A number of independently variable out-of-phase signals can be obtained from these 90 ° out-of-phase signals and this technique is better known as the vector sum method of phase shifting. Control signals to the inputs of the VGAs required to obtain 22.5 ° phase shifts were designed from simulations and are generated using 16-bit DACs. The design is implemented and manufactured using a 0.35 µm SiGe BiCMOS process and the complete prototype IC occupies an area of 2.65 × 2.65 mm2. The I/Q VCO with 360 ° variable phase outputs occupies 1.10 × 0.85 mm2 of chip area and the 16-bit DAC along with its decoding circuitry occupies 0.41 × 0.13 mm2 of chip area. The manufactured quadrature VCO was found to oscillate between 4.12 ~ 4.74 GHz and consumes 23.1 mW from a 3.3 V supply without its buffer circuitry. A maximum phase noise of -78.5 dBc / Hz at a 100 kHz offset and -108.17 dBc / Hz at a 1 MHz offset was measured and the minimum VCO figure of merit is 157.8 dBc / Hz. The output voltages of the 16 bit DAC are within 3.5 % of the design specifications. When the phase shifter is controlled by the 16 DAC signals, the maximum measured phase error of the phase shifter is lower than 10 %. / Dissertation (MEng)--University of Pretoria, 2009. / Electrical, Electronic and Computer Engineering / unrestricted