Distributed source coding (DSC) is a fundamental concept in information theory. It refers to distributed compression of correlated but geographically separated sources. With the development of wireless sensor networks, DSC has attracted great research interest in the recent years [26]. Although many channel code based DSC schemes have been developed (e.g., those based on turbo codes [11]and LDPC codes [20]), this thesis focuses on the arithmetic coding based approaches, namely, Distributed Arithmetic Coding (DAC) due to its simplicity in encoding [8]. To date, most of the DAC approaches that have been proposed deal with binary sources and can not handle non-binary cases. Little research has been done to extend DAC for non-binary sources. This work aims at developing efficient DAC techniques for the compression of non-binary sources. The key idea of DAC is representing the source symbols by overlapping intervals, as opposed to the case of conventional arithmetic coding where the intervals representing the symbols do not overlap. However the design of the overlapping intervals has been completely of heuristic nature to date. As such, the first part of this work is a thorough study of various interval-overlapping rules in binary DAC so as to understand how these rules impact the performance of DAC. The insight acquired in this study is used in the second part of this work, where two DAC algorithms are proposed to compress non-binary non-uniform sources. The first algorithm applies a designed overlap structure in DAC process, while the second converts a non-binary sequence into a binary sequence by Huffman Coding and encoding the result in binary DAC. Simulation studies are performed to demonstrate the efficiencies of the two proposed algorithms in a variety of source parameter settings.

The goal of this research is to design a low power, high speed, 10-bit, 250 MHz digital-to-analog converter. For high speed application, the DAC is implemented in thermometer-code based segmented DAC. An optimal switching scheme is used in this design. The switching scheme can compensate the gradient error in thermometer-code DAC arrays.This DAC is implemented in a 0.18£gm 1P6M mixed-signal CMOS process provided by TSMC.

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As the rapid evolution in semiconductor technology, transistors’ feature size has reached to 22nm and below, which brings great impact to analog and mixed-signal circuits. As the significant bridge connecting the analog world and digital system, data converter suffers from nonlinearity resulting from mismatch among its unit components. The smaller transistors are, the larger relative mismatch among them becomes. However, using larger transistors leads to more area cost and power consumption. Therefore, researchers have been working hard on how to alleviate the mismatch issue. In recent years, Dynamic Element Matching (DEM) becomes a popular approach that can significantly improve linearity, especially Spurious-free Dynamic Range (SFDR), of a data converter system. The basic idea of DEM is to shuffle the usage pattern of unit elements so that the mismatch error is no longer correlated to the input signal. Thus, DAC’s linearity will be improved. Generally, DEM Nyquist-rate DAC does mismatch scrambling, which smooths distortions resulting from mismatch into white noise. DEM Delta-Sigma DAC does mismatch shaping, which pushes distortions away from the signal band, typically lower frequencies. In this thesis, we focused on mismatch-shaping Delta-Sigma DACs. Two of those various algorithms are implemented logically and physically. With placement and routing information, we got more accurate result on the speed and power dissipation. The comparison shows the tradeoff among number of quantization levels, mismatch-shaping order, and hardware complexity. / text

This thesis includes two topics. The first one is the architecture as well as the circuit implementation of an ultra low-power direct digital frequency synthesizer (DDFS) based on the straight line approximation. The second one is the circuit implementation of the low-power DDFS with an error compensation. The proposed approximation technique replaces the conventional ROM-based phase-to-amplitude conversion circuitry and the linear digital-to-analog converter with a nonlinear digital-to-analog converter (DAC) to realize a simple approximation of the sine function. Thus, the overall power dissipation as well as hardware complexity can be significantly reduced. Besides, by adding the error compensation, the spurious-free dynamic range (SFDR) of the synthesized output signal can be raised drastically.

SAR-ADCs are very popular and suitable for conversions up to few tens of MHz with 8 to 12 bits of resolution. A very popular type is the Charge Redistribution SAR-ADC which is based on a capacitive array. Higher speeds can be achieved by using the interleaving technique where a number of SAR-ADCs are working in parallel. These speeds, however, can only be achieved if the reference voltage can cope with the switching of the capacitive array. In this thesis the design of a programmable voltage reference generator for a Charge Redistribution SAR-ADC was studied. A number of architectures were studied and one based on a Current Steering DAC was chosen because of the settling time that could offer to the Charge Redistribution SAR-ADC switching operation. This architecture was further investigated in order to spot the weak points of the design and try to minimize the settling time. In the end, the final design was evaluated and possible trimming techniques were proposed that could further speed up the design.

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CMOS Technology has advanced for decades under the rule of Moore's law. But all good things must come to an end. Researchers estimate that CMOS will reach a lower limit on feature size within the next 10 to 15 years. In order to assure further progress in the field, new computing architectures must be investigated. These nanoscale architectures are many and varied. It remains to be seen if any will become a legitimate successor to CMOS. Single electron tunneling is a process by which electrons can be trans- ported (tunnel) across a thin insulating surface. A conducting island sepa rated by a pair of quantum tunnel junctions creates a Single Electron Transistor (SET). SETs exhibit higher functionality than traditional MOSFETs, and function best at very small feature sizes, in the neighborhood of 1nm. Many circuits must be developed before SETs can be considered a viable contender to CMOS technology. One important circuit is the Digital to Analog Converter (DAC). DACs are present on many microprocessors and microcontrollers in use today and are necessary in many situations. While other SET circuits have been proposed, including ADCs, no DAC design exists in open literature. We propose three possible SET DAC designs and characterize them with an HSPICE SET simulation model. The first design is a charge scaling architecture similar to what is frequently used in CMOS. The second two designs are based on a current steering architecture, but are unique in their implementation with SETs. / Master of Science

The purpose of this thesis work was to investigate possible in-, on- or at-line methods to determine the degree of oxidation in dialdehyde cellulose. Several technologies were reviewed which led to a feasibility study into a possible on-line or at-line method using near infrared spectroscopy for determining the degree of oxidation in wet dialdehyde cellulose. A calibration model was built using the near infrared spectra of 19 samples created from kraft pulp with a degree of oxidation between 0 and 52.1 %. The obtained model uses five significant principal components and has a goodness of fit (R2) of 0.998 and a goodness ofprediction (Q2) of 0.991. The first principal component describes the degree of oxidation and the second the water content. A validation set of six samples was used to test the model and the predicted values resulted in a root mean square error of prediction of 0.85 in comparison with the reference method which had a pooled standard deviation of 0.69.

In light of escalating concerns over climate change and the imperative to mitigate greenhouse gas emissions, particularly carbon emissions, the pursuit of negative emissions technologies (NETs) has gained significant attention. Direct air capture (DAC) stands out as a promising avenue, offering the potential to actively remove carbon dioxide from the atmosphere. This degree project provides a thorough examination of two leading DAC projects, Mammoth and Stratos, which exemplify innovative approaches to achieving negative emissions at scale. By employing low-temperature DAC (LT DAC) and high-temperature DAC (HT DAC) respectively, Mammoth and Stratos confront the challenge of carbon capture with distinct technological strategies. This degree project employs a Techno-Economic Analysis (TEA) to estimate the Levelized Cost of CO2 Capture through DAC (LCOD), revealing Mammoth'sLCOD at $260/tCO2and Stratos at $608/tCO2, excluding costs for carbon transport and storage.The TEA is followed up with a Sensitivity Analysis to assess how the LCOD is affected by variations in input parameters, such as capital costs and electricity demand/costs among several parameters. Furthermore, this degree project identifies that uncertainties remain regarding the carbon storage solution, including its efficiency, long-term environmental implications, and associated costs. Given the Stratos projects’ dependence on Enhanced Oil Recovery (EOR) as the method of storing the captured carbon, the concern regarding efficiency and environmental implications is particularly relevant, as this method could potentially optimize oil production by 5-20%. As the discourse on DAC continues to evolve, this degree project advocates for the integration of Life Cycle Analysis (LCA) to comprehensively evaluate environmental impactsof both projects. This would guide the path towards sustainable carbon capture solutions, aiding in informed decision-making and guiding future DAC endeavors.