Hybrid stepper motors are a common type of electric motor used throughout industry thanks to its low-cost, high torque at low speed and open loop positioning capabilities. However, a closed loop control is often required for industrial applications with high precision requirements. The closed loop control can also be used to lower the power consumption of the motor and ensure that stalls are avoided. It is quite common to utilise a large and costly position encoder or resolver to feedback the position signal to the control logic. This thesis has explored the possibility of using a low-cost position sensor based on Hall elements. Additionally, a sensorless estimation algorithm, using only stator winding measurements, has been investigated both as a competitive alternative and as a possible complement to the position sensor. The thesis work summarises and discusses previous research attempts to adequately measure or estimate and control the hybrid stepper motors position and load angle without using a typical encoder or resolver. Qualitative results have been produced through simulations prior to implementation and experimental testing. The readings from the position sensor is subject to noise, owing to its resolution and construction. The position signal has been successfully filtered, improving its accuracy from 0.56° to 0.25°. The output from the sensorless estimation algorithm is subject to non-linear errors caused by errors in phase voltage measurements and processing of velocity changes. However, the dynamics are reliable at constant speeds and could be used for position control.

This dissertation reviews the theory of fast matrix multiplication from a multilinear-algebraic point of view, as well as recent fast matrix multiplication algorithms based on discrete Fourier transforms over nite groups. To this end, the algebraic approach is described in terms of group algebras over groups satisfying the triple product Property, and the construction of such groups via uniquely solvable puzzles. The higher order singular value decomposition is an important decomposition of tensors that retains some of the properties of the singular value decomposition of matrices. However, we have proven a novel negative result which demonstrates that the higher order singular value decomposition yields a matrix multiplication algorithm that is no better than the standard algorithm. / Mathematical Sciences / M. Sc. (Applied Mathematics)

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Este trabalho apresenta uma análise de algoritmos computacionais aplicados à estimação de fasores elétricos em SEPs. A medição dos fasores é realizada por meio da alocação de Unidades de Medição Fasorial nestes sistemas e encontra diversas aplicações nas áreas de operação, controle, proteção e planejamento. Para que os fasores possam ser aplicados, são definidos padrões de medição, sincronização e comunicação, por meio da norma IEEE C37.118.1. A norma apresenta os padrões de mensagens, timetag, fasores, sistema de sincronização, e define testes para avaliar a estimação. Apesar de abranger todos esses critérios, a diretriz não define um algoritmo de estimação padrão, abrindo espaço para uso de diversos métodos, desde que a precisão seja atendida. Nesse contexto, o presente trabalho analisa alguns algoritmos de estimação de fasores definidos na literatura, avaliando o comportamento deles em determinados casos. Foram considerados, dessa forma, os métodos: Transformada Discreta de Fourier, Método dos Mínimos Quadrados e Transformada Wavelet Discreta, nas versões recursivas e não-recursivas. Esses métodos foram submetidos a sinais sintéticos, a fim de verificar o comportamento diante dos testes propostos pela norma, avaliando o Total Vector Error, tempo de resposta e atraso e overshoot. Os algoritmos também foram embarcados em um hardware, denominado PC104, e avaliados de acordo com os sinais medidos pelo equipamento na saída analógica de um simulador em tempo real (Real Time Digital Simulator). / This work presents an analysis of computational algorithms applied to phasor estimation in Electrical Power Systems. The phasor estimation process uses the allocation of Phasor Measurement Units in the system and the measures can be used in many control, operation, planing and protection applications. Therefore, the power system phasors are very useful, specially if they have a common time reference, allowing the determination of the system\'s condition at a given time. The procedures necessary for power system\'s phasors estimation and application are defined by IEEE C37.118.1 standard. The standard defines the requirements for phasor estimation, presenting tests and a methodology to evaluate the algorithms performance. Thus, the standard defines the time tag and data patterns, some synchronization methods, and message examples, simplifying the communication requirements. Despite defining all these parts, the standard does not state which estimation algorithm should be used, making room for the use of various methods, since the standard precision is met. In this context, this work analyzes some phasor estimation algorithms defined in the literature, evaluating their behavior for some cases. It was adopted the recursive and non-recursive versions of the methods: Discrete Fourier Transform, Least Squares and Discrete Wavelet Transform. They were submitted to the standard signals, evaluating the Total Vector Error, time delays, and overshoots. The algorithms were also embedded in hardware (named PC104) and evaluated by real time simulated signals, measured by the PC104 using the analog outputs of a Real Time Digital Simulator.

Este trabalho apresenta uma análise de algoritmos computacionais aplicados à estimação de fasores elétricos em SEPs. A medição dos fasores é realizada por meio da alocação de Unidades de Medição Fasorial nestes sistemas e encontra diversas aplicações nas áreas de operação, controle, proteção e planejamento. Para que os fasores possam ser aplicados, são definidos padrões de medição, sincronização e comunicação, por meio da norma IEEE C37.118.1. A norma apresenta os padrões de mensagens, timetag, fasores, sistema de sincronização, e define testes para avaliar a estimação. Apesar de abranger todos esses critérios, a diretriz não define um algoritmo de estimação padrão, abrindo espaço para uso de diversos métodos, desde que a precisão seja atendida. Nesse contexto, o presente trabalho analisa alguns algoritmos de estimação de fasores definidos na literatura, avaliando o comportamento deles em determinados casos. Foram considerados, dessa forma, os métodos: Transformada Discreta de Fourier, Método dos Mínimos Quadrados e Transformada Wavelet Discreta, nas versões recursivas e não-recursivas. Esses métodos foram submetidos a sinais sintéticos, a fim de verificar o comportamento diante dos testes propostos pela norma, avaliando o Total Vector Error, tempo de resposta e atraso e overshoot. Os algoritmos também foram embarcados em um hardware, denominado PC104, e avaliados de acordo com os sinais medidos pelo equipamento na saída analógica de um simulador em tempo real (Real Time Digital Simulator). / This work presents an analysis of computational algorithms applied to phasor estimation in Electrical Power Systems. The phasor estimation process uses the allocation of Phasor Measurement Units in the system and the measures can be used in many control, operation, planing and protection applications. Therefore, the power system phasors are very useful, specially if they have a common time reference, allowing the determination of the system\'s condition at a given time. The procedures necessary for power system\'s phasors estimation and application are defined by IEEE C37.118.1 standard. The standard defines the requirements for phasor estimation, presenting tests and a methodology to evaluate the algorithms performance. Thus, the standard defines the time tag and data patterns, some synchronization methods, and message examples, simplifying the communication requirements. Despite defining all these parts, the standard does not state which estimation algorithm should be used, making room for the use of various methods, since the standard precision is met. In this context, this work analyzes some phasor estimation algorithms defined in the literature, evaluating their behavior for some cases. It was adopted the recursive and non-recursive versions of the methods: Discrete Fourier Transform, Least Squares and Discrete Wavelet Transform. They were submitted to the standard signals, evaluating the Total Vector Error, time delays, and overshoots. The algorithms were also embedded in hardware (named PC104) and evaluated by real time simulated signals, measured by the PC104 using the analog outputs of a Real Time Digital Simulator.

Processing of broadband signals induced on an antenna array using a tapped delay line filter and a set of steering delays has two problems. Firstly one needs to manipulate large matrices to estimate the filter coefficients. Secondly the use of steering delays is not only cumbersome but implementation errors cause loss of system performance. This thesis looks at both of these problems and presents elegant solutions by developing and studying a design method referred to as the DFT method, which does not require steering delays and is computationally less demanding compared to existing methods. Specifically the thesis studies and compares the performance of a time domain element space beamformer using the proposed method and that using an existing method, and develops the DFT method when the processor is implemented in partitioned form. The study presented in the thesis shows that the processors using the DFT method are robust to look direction errors and require less computation than that using the existing method for comparable performance. The thesis further introduces a broadband beamformer design which does not require any steering delays between the sensors and the tapped delay line section as is presently the case. It has the capability of steering the array in an arbitrary direction with a specified frequency response in the look direction while canceling unwanted uncorrelated interferences. The thesis presents and compares the performance of a number of techniques to synthesize an antenna pattern of a broadband array. These techniques are designed to produce isolated point nulls as well as broad sector nulls and to eliminate the need for the steering delays. Two of the pattern synthesis techniques presented in the thesis allow optimization against unwanted interferences in unknown directions. The techniques allow formulation of a beamforming problem such that the processor is not only able to place nulls in specified directions but also able to cancel directional interferences in unknown directions along with a specified frequency response in the look direction over a band of interest. The thesis also presents a set of directional constraints such that one does not need steering delays and an array can be constrained in an arbitrary direction with a specified frequency response. The constraints presented in the thesis are simple to implement. Based on these constraints a pattern synthesis technique for broadband antenna array is also presented.

The purpose of this research is to present a low-power wireless communication receiver with an enhanced performance by relieving the system complexity and performance degradation imposed by a quantization process. With an overwhelming demand for more reliable communication systems, the complexity required for modern communication systems has been increased accordingly. A byproduct of this increase in complexity is a commensurate increase in power consumption of the systems. Since the Shannon's era, the main stream of the methodologies for promising the high reliability of communication systems has been based on the principle that the information signals flowing through the system are represented in digits. Consequently, the system itself has been heavily driven to be implemented with digital circuits, which is generally beneficial over analog implementations when digitally stored information is locally accessible, such as in memory systems. However, in communication systems, a receiver does not have a direct access to the originally transmitted information. Since the received signals from a noisy channel are already continuous values with continuous probability distributions, we suggest a mixed-signal system in which the received continuous signals are directly fed into the analog demodulator and the subsequent soft-decision Viterbi decoder without any quantization involved. In this way, we claim that redundant system complexity caused by the quantization process is eliminated, thus gives better power efficiency in wireless communication systems, especially for battery-powered mobile devices. This is also beneficial from a performance perspective, as it takes full advantage of the soft information flowing through the system.

This thesis introduces spatial filtering, which is a technique to extend the time step size beyond the conventional stability limit for the Finite-Difference Time-Domain (FDTD) method, at the expense of transforming field nodes between the spatial domain and the discrete spatial-frequency domain and removing undesired spatial-frequency components at every FDTD update cycle. The spatially-filtered FDTD method is demonstrated to be almost as accurate as and more efficient than the conventional FDTD method via theories and numerical examples. Then, this thesis combines spatial filtering and an existing subgridding scheme to form the spatially-filtered subgridding scheme. The spatially-filtered subgridding scheme is more efficient than existing subgridding schemes because the former allows the time step size used in the dense mesh to be larger than the dense mesh CFL limit. However, trade-offs between accuracy and efficiency are required in complicated structures.

This thesis introduces spatial filtering, which is a technique to extend the time step size beyond the conventional stability limit for the Finite-Difference Time-Domain (FDTD) method, at the expense of transforming field nodes between the spatial domain and the discrete spatial-frequency domain and removing undesired spatial-frequency components at every FDTD update cycle. The spatially-filtered FDTD method is demonstrated to be almost as accurate as and more efficient than the conventional FDTD method via theories and numerical examples. Then, this thesis combines spatial filtering and an existing subgridding scheme to form the spatially-filtered subgridding scheme. The spatially-filtered subgridding scheme is more efficient than existing subgridding schemes because the former allows the time step size used in the dense mesh to be larger than the dense mesh CFL limit. However, trade-offs between accuracy and efficiency are required in complicated structures.

This dissertation reviews the theory of fast matrix multiplication from a multilinear-algebraic point of view, as well as recent fast matrix multiplication algorithms based on discrete Fourier transforms over nite groups. To this end, the algebraic approach is described in terms of group algebras over groups satisfying the triple product Property, and the construction of such groups via uniquely solvable puzzles. The higher order singular value decomposition is an important decomposition of tensors that retains some of the properties of the singular value decomposition of matrices. However, we have proven a novel negative result which demonstrates that the higher order singular value decomposition yields a matrix multiplication algorithm that is no better than the standard algorithm. / Mathematical Sciences / M. Sc. (Applied Mathematics)