Silicon Carbide devices are proving to be most promising for high power and high-temperature application in recent times. Efficient and accurate characterization of the device characteristics is key to the fabrication of high quality devices and reproduction of the quality of the devices fabricated. Capacitance-Voltage profiling is one of the most commonly used techniques to measure the doping profiles of semiconductors. However, interpretation of C-V profiling in the presence of traps in the material becomes complicated. Various complications arising from compensation between donors and acceptors, partial ionization of dopants and presence of deep level impurities could yield anomalous measured profile. Silicon Carbide being a wide bandgap semiconductor, many impurities commonly found such as Boron and Aluminum are not completely ionized at Room temperature. This leads to complications in calculating doping profiles when the trap levels are deeper. Other complications arising due to series resistance effect and diode edge effect may also affect the measured profile. Accounting for these complications may be difficult by mere observation of the measured profile. Simulation can be an excellent tool to extract parameters of interest from experimental results that are influenced by non-ideal effects. Fitting of the experimentally obtained data with simulated profile using specific models may be a useful technique to quantitatively account for the deviations from the actual profiles.

Silicon carbide is a very promising semiconductor material for high-power, highrequency, and high-temperature applications. SiC distinguishes from traditional narrow bandgap semiconductors, such as silicon, in that common doping impurities in SiC have activation energies larger than the thermal energy kT even at room temperature. This causes incomplete ionization of such impurities, which leads to strong temperature and frequency dependence of the semiconductor junction differential admittance and, if carrier freeze-out effects are not taken into account, errors in doping profiles calculated from capacitance-voltage data. Approaches commonly used to study the influence of incomplete impurity ionization on the junction admittance are based on the truncated space charge approximation and/or the small-signal approximation. The former leads to impurity ionization time constant and occupation number errors, while the latter fails if the measurement ac signal amplitude is larger than kT/q. In this work, a new reverse bias Schottky junction admittance model valid for the general case of an arbitrary temperature, measurement signal frequency and amplitude, and doping occupation number and time constant distributions is developed. Results of junction admittance calculations using the developed model are compared with the results of traditional models. Based on the general model, a new method of admittance spectroscopy data analysis is created and used to determine impurity parameters more accurately than allowed by traditional approaches. Incomplete impurity ionization is investigated for the case of nitrogen donors and aluminum and boron acceptors in 4H- and 6H-SiC. It is shown that the degree of carrier freeze-out is significant in heavily N-doped 6H-SiC and in Al- and B-doped SiC. Frequency dispersion of the junction admittance is shown to be significant at room temperature in N- and B-doped SiC. Junction capacitance calculations as a function of applied dc bias show that calculated doping profiles deviate from the actual impurity concentration profiles if the impurity ionization time constant is comparable with the ac signal period. This is the case for N- and B-doped SiC with certain values of the impurity activation energy and capture cross-section. Validity of the new model and its predictions are successfully tested on experimental admittance data for N- and B-doped SiC Schottky diodes.

Failure analysis and optimization of semiconducting devices request knowledge of their electrical properties. To meet the demands of today’s semiconductor industry, an electrical nanometrology technique is required which provides quantitative information about the doping profile and which enables scans with a lateral resolution in the sub-10 nm range. In the presented work it is shown that Kelvin probe force microscopy (KPFM) is a very promising electrical nanometrology technique to face this challenge. The technical and physical aspects of KPFM measurements on semiconductors required for the correct interpretation of the detected KPFM bias are discussed. A new KPFM model is developed which enables the quantitative correlation between the probed KPFM bias and the dopant concentration in the investigated semiconducting sample. Quantitative dopant profiling by means of the new KPFM model is demonstrated by the example of differently structured, n- and p-type doped silicon. Additionally, the transport of charge carriers during KPFM measurements, in particular in the presence of intrinsic electric fields due to vertical and horizontal pn junctions as well as due to surface space charge regions, is discussed. Detailed investigations show that transport of charge carriers in the semiconducting sample is a crucial aspect and has to be taken into account when aiming for a quantitative evaluation of the probed KPFM bias.

Failure analysis and optimization of semiconducting devices request knowledge of their electrical properties. To meet the demands of today’s semiconductor industry, an electrical nanometrology technique is required which provides quantitative information about the doping profile and which enables scans with a lateral resolution in the sub-10 nm range. In the presented work it is shown that Kelvin probe force microscopy (KPFM) is a very promising electrical nanometrology technique to face this challenge. The technical and physical aspects of KPFM measurements on semiconductors required for the correct interpretation of the detected KPFM bias are discussed. A new KPFM model is developed which enables the quantitative correlation between the probed KPFM bias and the dopant concentration in the investigated semiconducting sample. Quantitative dopant profiling by means of the new KPFM model is demonstrated by the example of differently structured, n- and p-type doped silicon. Additionally, the transport of charge carriers during KPFM measurements, in particular in the presence of intrinsic electric fields due to vertical and horizontal pn junctions as well as due to surface space charge regions, is discussed. Detailed investigations show that transport of charge carriers in the semiconducting sample is a crucial aspect and has to be taken into account when aiming for a quantitative evaluation of the probed KPFM bias.

Ce travail de thèse présente une étude concernant la caractérisation des effets électrothermiques dans les transistors bipolaires à hétérojonction (HBT) en SiGe. Lors de ces travaux, deux procédés technologiques BiCMOS à l’état de l’art ont été analysés: le B11HFC de Infineon Technologies (130nm) et le B55 de STMicroelectronics (55nm).Des structures de test dédiées ont étés conçues, pour évaluer l’impact électrothermique du back end of line (BEOL) de composants ayant une architecture à un ou plusieurs doigts d’émetteur. Une caractérisation complète a été effectuée en régime continu et en mode alternatif en petit et en grand signal. De plus, une extraction des paramètres thermiques statiques et dynamiques a été réalisée et présentée pour les structures de test proposées. Il est démontré que les figures de mérite DC et RF s’améliorent sensiblement en positionnant des couches de métal sur le transistor, dessinées de manière innovante et ayant pour fonction de guider le flux thermique vers l’extérieur. L’impact thermique du BEOL a été modélisé et vérifié expérimentalement dans le domaine temporel et fréquentiel et aussi grâce à des simulations 3D par éléments finis. Il est à noter que l’effet du profil de dopage sur la conductivité thermique est analysé et pris en compte.Des topologies de transistor innovantes ont étés conçues, permettant une amélioration des spécifications de l’aire de sécurité de fonctionnement, grâce à un dessin innovant de la surface d’émetteur et du deep trench (DTI).Un modèle compact est proposé pour simuler les effets de couplage thermique en dynamique entre les émetteurs des HBT multi-doigts; ensuite le modèle est validé avec de mesures dédiées et des simulations TCAD.Des circuits de test ont étés conçus et mesurés, pour vérifier la précision des modèles compacts utilisés dans les simulateurs de circuits; de plus, l’impact du couplage thermique entre les transistors sur les performances des circuits a été évalué et modélisé. Finalement, l’impact du dissipateur thermique positionné sur le transistor a été étudié au niveau circuit, montrant un réel intérêt de cette approche. / This work is focused on the characterization of electro-thermal effects in advanced SiGe hetero-junction bipolar transistors (HBTs); two state of the art BiCMOS processes have been analyzed: the B11HFC from Infineon Technologies (130nm) and the B55 from STMicroelectronics (55nm).Special test structures have been designed, in order to evaluate the overall electro-thermal impact of the back end of line (BEOL) in single finger and multi-finger components. A complete DC and RF electrical characterization at small and large signal, as well as the extraction of the device static and dynamic thermal parameters are performed on the proposed test structures, showing a sensible improvement of the DC and RF figures of merit when metal dummies are added upon the transistor. The thermal impact of the BEOL has been modeled and experimentally verified in the time and frequency domain and by means of 3D TCAD simulations, in which the effect of the doping profile on the thermal conductivity is analyzed and taken into account.Innovative multi-finger transistor topologies are designed, which allow an improvement of the SOA specifications, thanks to a careful design of the drawn emitter area and of the deep trench isolation (DTI) enclosed area.A compact thermal model is proposed for taking into account the mutual thermal coupling between the emitter stripes of multi-finger HBTs in dynamic operation and is validated upon dedicated pulsed measurements and TCAD simulations.Specially designed circuit blocks have been realized and measured, in order to verify the accuracy of device compact models in electrical circuit simulators; moreover the impact on the circuit performances of mutual thermal coupling among neighboring transistors and the presence of BEOL metal dummies is evaluated and modeled.