The scope for this thesis was to design a debug interface for a DSP (digital signal processor). The DSP is a research version of a Motorola 56000 that is designed for a project on asynchronous processor and for use in education. The DSP and debug interface are controlled via a standard PC with RS232 interface equipped with Linux operation system. In the project 4 blocks has been designed: The first block can set the DSP core in debug mode or run mode. The second block sends a debug instruction to the DSP core, these debug instructions were prerequisite to the project. The third block enable read and write connection to the memory buses between the DSP core and the three memory blocks. The forth block can override the control signals to the memories from the DSP core. The project also uses an UART for interpreting and sending control signals and data between the different blocks and the computer. A text terminal program for Linux has also been programmed for handling the PC side communication. The hardware has been constructed and tested together with a dummy DSP core and dummy memories, but it has not been tested together with the live DSP core. The Linux program has been tested the same way and seems to do what it's supposed to, though it leaves a lot work to be easy to handle.

Ogg Vorbis is a fairly new and growing audio format, often used for online distribution of music and internet radio stations for streaming audio. It is considered to be better than MP3 in both quality and compression and in the same league as for example AAC. In contrast with many other formats, like MP3 and AAC, Ogg Vorbis is patent and royalty free. The purpose of this thesis project was to investigate how the C6416 DSP processor and a Stratix II FPGA could be connected to each other and work together as co-processors and using an Ogg Vorbis decoder as implementation example. A fixed-point decoder called Tremor (developed by Xiph.Org the creator of the Vorbis I specification), has been ported to the DSP processor and an Ogg Vorbis player has been developed. Tremor was profiled before performing the software / hardware partitioning to decide what parts of the source code of Tremor that should be implemented in the FPGA to off-load and accelerate the DSP.

Variable speed drive technology has advanced dramatically in the last 10 years with the advent of new power devices. In this study, a three phase induction motor drive using Insulated Gate Bipolar Transistors (IGBT) at the inverter power stage is introduced to implement speed and position control for the revolving stage in the Frederic Wood Theatre This thesis presents a solution to control a 3-phase induction motor using the Texas Instruments (TI) Digital Signal Processor (DSP) TMS320F2407A. The use of this DSP yields enhanced operations, fewer system components, lower system cost and increased efficiency. The control algorithm is based on the constant volts-per-hertz principle because the exact speed control is not needed. Reflective object sensors which are mounted on concrete frame are used to detect accurate edge position of revolving stage. The sinusoidal voltage waveforms are generated by the DSP using the space vector modulation technique. In order to satisfy some operating conditions for safe and agreeable operation, a look-up table, which is used to give command voltage and speed signals in software, is applied to limit the maximum speed and acceleration of the revolving stage. Meanwhile, a boost voltage signal is added at the low frequency areas to make the motor produce maximum output torque when starting. A test prototype is then built to validate the performance. Several tests are implemented into the IGBT drive to explore the reason for unacceptable oscillations in IGBT’s gate control signals. Improvement methods in hardware layout are suggested for the final design.

Otoacoustic Emissions (OAE) are minute acoustic responses originating from the cochlea as a result of an external acoustic stimulus and are recorded using a sensitive microphone placed in the ear canal. OAEs are acquired by synchronous stimulation with an acoustic click or tone burst and recording of the post-stimulus responses. This method of acquiring OAEs is known as transient evoked otoacoustic emissions (TEAOE) and is commonly used in clinics as a screening method for hearing and cochlear functionality in infants. Recently, a novel method of acquiring OAEs utilizing a swept-tone, or chirp, as a stimulus was developed. This method used a deconvolution process to compress the swept tone response into an impulse or click-like response. Because the human ear does not hear all frequencies (pitches) at equal loudness the swept-tone stimulus was equalized in amplitude with respect to frequency. This equalized stimulus will be perceived by the ear as equally loud in all frequencies. In this study a new hearing level equalized stimulus was designed and the OAE responses were analyzed and compared to conventional click evoked OAEs. The equalized swept-tone stimulus evoked greater magnitude OAE responses when compared to the conventional methods. It was also able to evoke responses in subjects that had little TEOAEs which might fail conventional hearing screening.

Modern high-performance digital signal processing (DSP) applications face constantly increasing performance requirements and are becoming increasingly challenging to develop and work with. In DSP paradigm, many researchers see potential in achieving algorithm speed-up by employing Field Programmable Gate Arrays (FPGAs) – reconfigurable hardware with parallelism feature. However, developing applications for FPGAs incur particular challenges on the development flow. This work proposes a scalable hybrid DSP system for performing high-performance signal processing applications. The system employs hybrid CPU + FPGA architecture of commercially available, off-the-shelf (COTS) FPGAs and central processing units (CPU) of personal computers. In this work an example implementation of a multi-channel cross-correlator is investigated and delivered using a new development paradigm. The correlator is implemented on the XD1000 development system using a high-level FPGA programming tool – Impulse CoDeveloper. Analysis of DSP application development in a hybrid CPU+FPGA system employing the high-level programming tool Impulse C is presented. Potential of the selected tool to deliver algorithm speed-ups is investigated using reference multi-channel correlator software. Particular attention is devoted to input/output (I/O) implementation, which is considered one of the most challenging problems in FPGA design development. This work delivers an I/O framework based on PCI Express interface for the proposed high-performance scalable DSP system. Using Stratix II GX PCI Express Development Board from Altera Corporation, a scalable and flexible communication approach for the multi-channel correlator is delivered. This framework can be adapted to perform other high-performance streaming DSP applications. The outcomes of this work are a multi-channel correlator developed in a reconfigurable environment with new design methodology and I/O framework with software control application. The outcomes are used to demonstrate the potential of implementing DSP applications in hybrid CPU + FPGA architecture and to discuss existing challenges and suggest possible solutions.

Αντικείμενο της εργασίας είναι η δημιουργία ενός ολοκληρωμένου συστήματος με DSP για λήψη, κωδικοποίηση σύμφωνα με το πρότυπο JPEG και αποστολή εικόνας με τη βοήθεια του πρωτοκόλλου TCP/IP. Η ανάπτυξη της εφαρμογής έγινε σε γλώσσα προγραμματισμού c, ενώ ο έλεγχος του συστήματος γίνεται μέσω ενός γραφικού περιβάλλοντος αλληλεπίδρασης με το χρήστη. Στο πρώτο κεφάλαιο περιγράφεται η αναπτυξιακή πλατφόρμα DSK C6416T. Γίνεται αναφορά στην αρχιτεκτονική του επεξεργαστή ψηφιακού σήματος TMSC3206416T της εταιρείας Texas Instruments καθώς και στις υπόλοιπες περιφερειακές συσκευές. Στο δεύτερο κεφάλαιο περιγράφεται η αρχιτεκτονική της θυγατρικής κάρτας DSKeye Gigabit της εταιρείας Bitec, που συνδέεται στο DSK. Η κάρτα αυτή διαχειρίζεται τα δεδομένα για την αποστολή τους μέσω TCP/IP, καθώς και την έγχρωμη κάμερα OV5610 της εταιρείας Omnivision, η οποία είναι απαραίτητη για τη λήψη των εικόνων. Περιγράφεται επίσης ο τρόπος διασύνδεσης όλων των συσκευών από άποψη υλικού, ενώ στη συνέχεια περιγράφεται και η διασύνδεση λογισμικού. Στο τρίτο κεφάλαιο γίνεται αναλυτική περιγραφή του προτύπου JPEG, ιδιαίτερα του τμήματος που αναφέρεται στο Baseline DCT. Ακολουθεί παράδειγμα με το οποίο γίνεται κατανοητή η διαδικασία κωδικοποίησης σύμφωνα με το JPEG πρότυπο. Στο τέταρτο κεφάλαιο περιγράφεται η υλοποίηση του συστήματος, το διάγραμμα ροής του βασικού προγράμματος ενώ παρουσιάζονται τα αποτελέσματα με τη βοήθεια του γραφικού περιβάλλοντος. Τέλος στο παράρτημα αναφέρονται τα είδη EDMA μεταφορών και τρόποι προγραμματισμού. / This master thesis main purpose is to create a complete system using a DSP, for capturing images, encoding them according to the ISO/IEC 10918-1 specification widely known as JPEG and sending them to a remote client using the TCP/IP protocol. The source code was developed using the c programming language and a GUI was built in order to act as the remote client and also to control the capturing procedure. In the first chapter we review the C6416T DSP starter kit module, which incorporates the Texas Instruments 1GHz TMS320C6416T processor. In the next chapter we analyse the DSKeye gigabit daughtercard made by Bitec. This board features a 5.2 Megapixel colour camera used for capturing the desired images in Bayern format and also a gigabit Ethernet interface, allowing us to establish the TCP/IP communication. The following chapter explains the theoretical aspects of a baseline DCT JPEG encoder, laying emphasis on the details of the encoding procedure. Finally we present the flow charts and we summarise our results. The current project is a follow up to Bitec’s “webview” example, which uses the above hardware in order to capture and send a true colour bitmap image to a web browser. We used the DSKeye API with slight modifications in order to overcome memory restrictions imposed by image resolution and overall code size. The TCP stack was accessed using the BSD socket API. The encoder was ported to the DSP from the free JPEG c code available from the Independent JPEG Group. It was developed and tested using Microsoft’s Visual Studio 2005 Express Edition as well as TI’s Code Composer Studio v3.1. Finally the GUI was created using Labview 8.0.

Η παρούσα διπλωματική εργασία ασχολείται με την μελέτη αλγόριθμου συγχρονισμού σε OFDM συστήματα. Στα πρώτα δύο κεφάλαια αναλύονται χαρακτηριστικά και τεχνικές της OFDM διαμόρφωσης καθώς και η επίδραση του προσθετικού θορύβου. Στο τρίτο κεφάλαιο αναλύεται η ακολουθία συγχρονισμού. Στη συνέχεια παρουσιάζεται η τεχνική της αυτοσυσχέτισης και ο υπολογισμός του κατωφλίου που σηματοδοτεί το σημείο συγχρονισμού στο δέκτη. Στο πέμπτο κεφάλαιο γίνεται η παρουσίαση των τεχνικών που χρησιμοποιήθηκαν υλοποιημένες με τεχνικές VLSI. Αναφορά στα αποτελέσματα γίνεται στο έκτο κεφάλαιο, ενώ στο αμέσως επόμενο αναλύεται η πολυπλοκότητα, οι επιδόσεις του συστήματος και τα αποτελέσματα που προέκυψαν από την δοκιμή του συστήματος σε FPGA. Στο όγδοο και τελευταίο κεφάλαιο καταγράφονται τα συμπεράσματα που προέκυψαν από την μελέτη και εξομοίωση των τεχνικών που χρησιμοποιήθηκαν. / This thesis deals with the study of synchronization algorithm in OFDM systems. In the first two chapters analyze characteristics and techniques of OFDM modulation and the effect of additive noise. The third chapter discusses the synchronization sequence. Then, the autocorrelation technique and calculation of the threshold that marks the point of synchronization at the receiver. The fifth chapter is to present the techniques used implemented with VLSI techinques. Report on the results is the sixth chapter, while the next deals with the complexity, the system performance and the results obtained from testing the system in FPGA. In the eighth and final chapter, the conclusions drawn from the study and simulation techniques used.

This thesis examines the application of Digital Signal Processing (DSP) techniques, and specifically Wavelets, to the field of automatic coin recognition. The aim is to utilise DSP techniques to exploit information that is contained within time domain signals representing coins, which can not be accessed by other means. Attention is also given to the power requirement of possible solutions, with a low power solution being a secondary aim, as the solutions are targeted for use in a line-powered payphone. An examination of existing coin recognition techniques is presented, for which an improved but basic DSP coin recognition scheme using peak and trough location, is achieved. This is then improved using more advanced DSP techniques to access previously unavailable information contained within the signals. The advanced DSP techniques are developed into an integrated framework for automatic coin recognition. The framework is used to identify a single Wavelet solution that supplies a DSP representation of a set of coins. The representations of different coin types exist within a region of n-dimensional Euclidean space, which the framework attempts to locate uniquely for each coin type. To enable the framework to operate successfully, a key feature presented is the resampling of the waveforms input into the framework, to normalise any temporal variations in the input data. The location of the single Wavelet for analysis can not be achieved analytically and so is obtained using a novel Data Mining solution to search a Wavelet dictionary for possible solutions. This thesis proves that utilisation of the time localisation properties of the Discrete Wavelet Transform is possible when taken together with a distance metric strategy. Appropriate results are presented to verify the performance of the Wavelet solutions provided by the framework, especially in respect of counteracting fraudulent coins in the recognition process. As an overall validation of the research solution, an emulation of the coin recognition system was produced that could validate coins in real time, this is also documented. Both the hardware and software components of the integrated framework which have been developed, are fully modular and hold significant potential for expansion and integration into newer, more powerful cost effective coin recognition systems.

Submitted by Diogo Barreiros (diogo.barreiros@ufba.br) on 2017-02-17T14:50:27Z No. of bitstreams: 1 DissertacaoMscEdnaldo.pdf: 18094265 bytes, checksum: abe612737a6df2686311f28fc738d312 (MD5) / Approved for entry into archive by Vanessa Reis (vanessa.jamile@ufba.br) on 2017-02-17T15:02:35Z (GMT) No. of bitstreams: 1 DissertacaoMscEdnaldo.pdf: 18094265 bytes, checksum: abe612737a6df2686311f28fc738d312 (MD5) / Made available in DSpace on 2017-02-17T15:02:35Z (GMT). No. of bitstreams: 1 DissertacaoMscEdnaldo.pdf: 18094265 bytes, checksum: abe612737a6df2686311f28fc738d312 (MD5) / NESTE Trabalho apresenta-se a metodologia para concep¸c˜ao de equipamento para estudo da eletrofisiologia card´ıaca, desenvolvendo uma interface de hardware/software capaz de adquirir, tratar e exibir os sinais biom´edicos do cora¸c˜ao. Requisitos de projeto como o baixo custo, a portabilidade, a compatibilidade eletromagn´etica e a isola¸c˜ao galvˆanica da rede el´etrica foram estabelecidos, por´em foram respeitadas todas as regras de ergonomia, amostragem, filtragem e padroniza¸c˜ao da representa¸c˜ao gr´afica do eletrocardiograma (ECG) visando atender as normas vigentes. Para tanto, uma breve introdu¸c˜ao sobre a ´area de Eletrocardiografia foi realizada, contextualizando o presente Trabalho. O sistema ´e composto por trˆes subsistemas principais: um hardware microcontrolado que capta o sinal de trˆes deriva¸c˜oes de ECG atrav´es de eletrodos colocados na superf´ıcie do corpo do paciente e os transmite a um computador pessoal (PC) remoto por tecnologia sem fio (wireless); um firmware residente no n´ucleo do sistema, um DSP (Digital Signal Processor), respons´avel pelo gerenciamento do sistema, pelo c´alculo num´erico e pelo processamento digital de sinais; e um software, escrito em linguagem C++ (sistema operacional Windows), executado no PC respons´avel pela visualiza¸c˜ao e padroniza¸c˜ao dos dados adquiridos. Este trabalho contempla tamb´em um estudo do protocolo Bluetooth, para a forma¸c˜ao de redes wireless com os equipamentos desenvolvidos, com o objetivo de monitorar o comportamento card´ıaco de v´arios pacientes em um ´unico ponto de concentra¸c˜ao.

Maintenance of staff training continues to be problematic at agencies that serve individuals with developmental disabilities, due to high client to staff ratios, staff turnover and lack of time and resources for training. The purpose of this study was to find a refresher method that staff could independently access that would be effective, as well as convenient and non-aversive. Seven staff participants at a day program for adults with developmental disabilities were trained on two client intervention plans using a Behavioral Skills Training (BST) method. Each group was given follow-up training: one group received a video refresher; one utilized flashcards and one served as the control group. All participants increased correct responses after BST training. While all participants also maintained a higher percentage of correct responses after maintenance training, all of the video and one of the flashcard group participants exhibited higher scores in the last few months of the study than did the control group. Participant surveys revealed that the videos were the most preferred method of maintenance training; participants thought they would be most likely to independently access videos over flashcards, if the resources were made available.