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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Carrier Synchronization in a Digital Radio System

Cheung, David 04 1900 (has links)
Page 139 not included in the thesis. / <p> The problem of coherent carrier recovery and the effects of phase error on the performance of an offset quadrature-phase-shift-keying (QPSK) duobinary system have been investigated in the thesis. The system of interest is similar to RD -3 digital system that is being developed and installed as an efficient high data-rate digital radio communication system by Bell Northern Research Laboratory (BNR). </p> <p> Four carrier regeneration loop structures are investigated and analysed in the thesis. These are: (i) estimate-aided suppressed carrier loop (ii) decision-directed feedback loop (iii) shifted decision-directed feedback loop (iv) half-shifted decision-directed feedback loop All of these loop structures employ the technique of data-aided carrier synchronization. The estimate-aided loop structure exhibits steadystate behavior similar to that of a conventional Costas loop. The remaining three loop structures differ from the estimate-aided loop in the sense that they require decisions to make on the noisy received signal. These are then fedback to the carrier recovery circuit in such a way as to create a spectral line at carrier frequency. The loop behavior in the presence of additive noise has been investigated in some detail. For each loop, analytical expressions for the phase detector characteristic (S-curve) and the steady-state phase error probability density function (pdf) are derived, and provide a means of comparing the performance of the different recovery schemes.</p> / Thesis / Master of Engineering (MEngr)
2

Advanced modulation formats for high-bit-rate optical networks

Haris, Muhammad 07 May 2008 (has links)
The objective of the proposed research is to investigate the performance of advanced modulation formats, specifically modified duobinary return-to zero (MD-RZ) modulation scheme and its long-haul repeaterless transmission over standard single mode fiber (SMF). This research also focuses on phase modulation formats like differential phase shift keying (DPSK) and differential quadrature phase shift keying (DQPSK), specifically free spectral range (FSR) optimization and wavelength offset tolerance in direct detection of these phase modulated systems. In this research we present a novel and cost effective technique to generate a modified duobinary return-to-zero (MD-RZ) signal. Next, we attained experimental results for single channel and WDM repeaterless transmission using these MD-RZ signals. A numerical comparison is also drawn with other conventional MD-RZ transmitters. MD-RZ transmission characteristics are also studied numerically for 40 Gb/s WDM signals and compared with other two leading constant intensity phase modulated formats like DPSK and DQPSK. We also have presented experimental results for FSR optimization of DQPSK de-modulator for ultra-high data-rate systems in the presence of strong optical filtering. Choice of an optimal FSR beyond 1-bit delay in Mach-Zehnder delay interferometer (MZ-DI) helps relieving some of the degradations due to strong optical filtering. Wavelength offset tolerance is also experimentally measured and numerically investigated for DPSK and DQPSK modulation formats with different transmitter schemes employing intensity or phase modulators to achieve required phase shifts.
3

Highly digital power efficient techniques for serial links

Inti, Rajesh 28 November 2011 (has links)
Low power, high speed serial transceivers are employed in a wide range of applications ranging from chip-to-chip, backplane, and optical interconnects. Apart from being capable of handling a wide range of data rates, the transceivers should have low power consumption (mW/Gbps) and be fully integrated. This work discusses enabling techniques to implement such transceivers. Specifically, three designs: (1) a 0.5-4 Gbps serial link which uses current recycling to reduce power dissipation and (2) a 0.5-2.5 Gbps reference-less clock and data recovery circuit which uses a novel frequency detector to achieve unlimited acquisition range and (3) a 2-4 Gbps low power receiver architecture capable of resolving multiple signalling formats with a simplified XOR based phase rotating PLL will be presented. All the three circuit topologies are highly digital and aim to address the requirements of wide operating range, low power dissipation while being fully integrated. Measured results obtained from the prototypes illustrate the effectiveness of the proposed design techniques. / Graduation date: 2012 / Access restricted to the OSU Community at author's request from Dec. 2, 2011 - June 2, 2012

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