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Conventional computing based on classical technologies is approaching its limits. Therefore scientists are starting to consider the applications of quantum mechanics as a means for constructing more powerful computers. After proposing theoretical methods, many experimental setups have been designed to achieve quantum computing in reality. This thesis gives some background information on the subject of quantum computing. We first review the concept of quantum entanglement, which plays a key role in quantum computing, and then we discuss the physics of the SQUIDs-cavity method proposed by Yang et al., and give the definitions of quantum gates which are the elements that are needed to construct quantum circuits. Finally we give an overview of recent developments of SQUIDs-cavity systems and quantum circuits after Yang et al.'s proposal in 2003. These new developments help to take a step towards the constructions of higher levels of quantum technologies, e.g. quantum algorithms and quantum circuits.

In light of the growing TV industry in Sweden competition is intensified. Production companies have increased in number and public service has gone through major organizational changes in order to adapt to the new market conditions. Stockholm is the major cluster for TV production. As a consequence production firms are located there. The thesis reveals that competition has risen and a certain trend of specialization has taken place. The Swedish public television provider has increased its collaboration with other production companies and also exports its own formats. As quality plays a crucial part in TV production it is relevant to understand the stakeholders and their definition of the concept of quality in relation to production and what role it plays in the interconnection between the decision makers and the creators. This thesis addresses two subjects. First the geographic nature of the Swedish TV industry: Its location, district and the network within the Stockholm region. Second the concept of quality and how the different stakeholders’ within the Stockholm region define quality in TV production. Using qualitative interviews similarities and differences in the concept of quality were discovered. The major differences are related to stakeholders’ relation to the cultural and economic spheres. Two formats were singled out for comparison: Reality shows and TV-series (all genres).  Firstly gate-keepers definitions in relation to formats and genres are analyzed through interviews. Secondly a participatory observation of the Swedish drama series Real Humans was conducted. By observing and interacting with the production and those involved the concept of quality is addressed in the creative context. I argue that there are similarities in the conceptualization of quality between different stakeholders but differences when prioritizing and crafting quality. Hence there is a complexity in the definition within TV-production which is identified and discussed in this thesis. / quality, TV-industry, gate-keeper, network

Die kontinuierliche Skalierung der planaren MOSFETs war in den vergangenen 40 Jahren der Schlüssel, um die Bauelemente immer kleiner und leistungsfähiger zu gestalten. Hinzu kamen Techniken zur mechanischen Verspannung, Verfahren zur Kurzzeitausheilung, die in-situ-dotierte Epitaxie und neue Materialien, wie das High-k-Gateoxid in Verbindung mit Titannitrid als Gatemetall. Jedoch erschwerten Kurzkanaleffekte und eine zunehmende Streuung der elektrischen Eigenschaften die Verkleinerung der planaren Transistoren erheblich. Somit gelangten die planaren MOSFETs mit der aktuellen 28 nm-Technologie teilweise an die Grenzen ihrer Funktionalität. Diese Arbeit beschäftigt sich daher mit der Integration von Multi-Gate-Transistoren auf Basis einer 22 nm-Technologie, welche eine bessere Steuerfähigkeit des Gatekontaktes aufweisen und somit die Fortführung der Skalierung ermöglichen. Zudem standen die Anforderungen eines stabilen und kostengünstigen Herstellungsprozesses als Grundvoraussetzung zur Übernahme in die Volumenproduktion stets mit im Vordergrund. Die Simulationen der Tri-Gate-Transistoren stellten dabei den ersten Schritt hin zu einer Multi-Gate-Technologie dar. Ihre Prozessabfolge unterscheidet sich von den planaren Transistoren nur durch die Formierung der Finnen und bietet damit die Möglichkeit eines hybriden 22 nm-Prozesses. Am Beispiel der Tri-Gate-Transistoren wurden zudem die Auswirkungen der Kristallorientierung, der mechanischen Verspannung und der Überlagerungseffekte es elektrischen Feldes auf die Leistungsfähigkeit von Multi-Gate-Strukturen analysiert. Im nächsten Schritt wurden Transistoren mit vollständig verarmten Kanalgebieten untersucht. Sie weisen aufgrund einer niedrigen Kanaldotierung eine Volumeninversion, eine höhere Ladungsträgerbeweglichkeit und eine geringere Anfälligkeit gegenüber der zufälligen Dotierungsfluktuation auf, welche für leistungsfähige Multi-Gate-Transistoren entscheidende Kriterien sind. Zu den betrachteten Varianten zählen die planaren ultradünnen SOI-MOSFETs, die klassischen FinFETs mit schmalen hohen Finnen und die vertikalen Nanowire-Transistoren. Anschließend wurden die Vor- und Nachteile der verschiedenen Transistorstrukturen für eine mittel- bis langfristige industrielle Nutzung betrachtet. Dazu erfolgte eine Analyse der statistischen Schwankungen und eine Skalierung hin zur 14 nm-Technologie. Eine Zusammenfassung aller Ergebnisse und ein Ausblick auf die mögliche Übernahme der Konzepte in die Volumenproduktion schließen die Arbeit ab. / Within the past 40 years the continuous scaling of planar MOSFETs was key to shrink the devices and to improve their performance. Techniques like mechanical stressing, rapid thermal annealing and in-situ doped epitaxial growing as well as novel materials, such as high-k-gate-oxide in combination with titanium nitride as metal-gate, has been introduced. However, short-channel-effects and increased scattering of electrical proper-ties significantly complicate the scaling of planar transistors. Thus, the planar MOSFETs gradually reached their limits of functionality with the current 28 nm technology node. For that reason, this work focuses on integration of multi-gate transistors based on a 22 nm technology, which show an improved gate control and allow a continuous scaling. Furthermore, the requirements of a stable and cost-efficient process as decisive condition for mass fabrication were always taken into account. The simulations of the tri-gate transistors present the first step toward a multi-gate technology. The process sequence differs from the planar one solely by a fin formation and offers the possibility of a hybrid 22 nm process. Also, the impact of crystal orientation, mechanical stress and superposition of electrical fields on the efficiency of multi-gate structures were analyzed for the tri-gate transistors. In a second step transistors with fully depleted channel regions were studied. Due to low channel doping they are showing a volume inversion, a higher carrier mobility and a lower sensitivity to random doping fluctuations, which are essential criteria for powerful multi-gate transistors. Reviewed structure variants include planar ultra-thin-body-SOI-MOSFETs, classic FinFETs with a tall, narrow fins and vertical nanowire transistors. Then advantages and disadvantages of the considered transistor structures have been observed for a medium to long term industrial use. For this purpose, an analysis of statistical fluctuations and the scaling-down to 14 nm technology was carried out. A summary of all results and an outlook to the transfer of concepts into mass fabrication complete this work.

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A lot of work has been done over the last decade on the logic synthesis and technology mapping of field programmable gate arrays (FPGAs) based on a single size of lookup table (LUT). A significant part of the FPGA market is occupied by devices based on more than one type of lookup tables. Examples of these heterogeneous LUT-based FPGAs are the Xilinx 4000 series devices. The technology mapping for this class of FPGAs has hardly been considered. This thesis covers work on the synthesis for heterogeneous LUT-based FPGAs. The proposed scheme uses the typical steps of graph covering, decomposition, node elimination and Boolean graph simplification. The covering step is based on the concept of flow networks and cut-computation. A theory is devised that reduces the flow network sizes so that a dynamic programming approach can be used to compute the feasible cuts in the network. An iterative selection algorithm can then be used to compute the set cover of the network. For the decomposition, the conventional bin-packing (cube-packing) algorithm has been extended so that it produces two types of bins. It has also been enhanced to explore several packing possibilities and include cube division and cascading of nodes. The classical functional decomposition method is extended to heterogeneous graphs. In particular, variable partitioning is coupled with other decomposition methods and exploits the structure of the functions. Partial collapsing and re-decomposition are used to re-synthesise the graphs. A strategy for eliminating nodes within a heterogeneous graph is developed. A simplification strategy is also derived from logic optimisation techniques. Comparisons of the mapping results on Xilinx devices show an improvement of over 11% over existing mapping tools for the same devices.

Current approaches to supporting module-based FPGA reconfiguration focus on various aspects and sub-problems in the area but do not combine to form a coherent, top-down methodology that factors low-level device parameters into every step of the design flow. This thesis proposes such a top-down methodology from application specification to low-level implementation, centered around examining the problem of generating a point-to-point communications infrastructure to support the changing interfaces of dynamically placed modules. Low-level implementation parameters are considered at every stage to ensure that area, timing and budget constraints of the application are met. The approach advocates the regular layout of modules surrounded by a wiring harness supporting the communications for those modules, and thus provides an advanced understanding of how to implement the "fixed wiring harness" model of reconfigurable computing proposed by Brebner. Results have shown that compared to flattened net lists the regularity of the layout does not impose significant overheads on critical path delays. At high communication densities it can even result in lower delays. The core of the methodology is an infrastructure generation process that allocates modules to slots and merges configuration graphs to form wiring harnesses that support the communications for these merged configurations. This thesis suggests methods and evaluates algorithms for configuration graph merging so as to reduce run-time reconfiguration overheads. Initial experiments with a greedy merging algorithm performed on an optical flow application resulted in a substantial reduction of 64% in reconfiguration time. The effects of graph merging with the initial greedy algorithm and an improved dynamic programming algorithm were explored for a range of device sizes and architectural parameters. Results show that configuration merging using the greedy method results in significant reductions to the reconfiguration delay. The dynamic programming algorithm provides consistent improvements above and beyond the savings provided by the greedy method. In addition, a strong correlation was identified between the quality of front-end design activities such as partitioning and the effectiveness of back-end implementations. The methodology is integrated into the Xilinx commercial tool flow for partial reconfiguration, and is effective for implementing applications for module-based FPGA reconfiguration where the modules and their communications requirements are known at design time. It also allows a system designer to consider alternate device sizes and parameters until a set is found that satisfies the application constraints.

Robust object tracking plays a central role in many applications of image processing, computer vision and automatic control. In this thesis, robust object tracking under complex environments, including heavy clutters in the background, low resolution of the image sequences and non-stationary camera, has been studied. The interest of this study stems from the improvement of the performance of visual tracking using particle filtering. A Geometric Active contour-based Tracking Estimator, namely GATE, has been developed in order to tackle the problems in robust object tracking where the existence of multiple features or good object detection is not guaranteed. GATE combines particle filtering and the level set-based active contour method. The particle filtering method is able to deal with nonlinear and non-Gaussian recursive estimation problems, and the level set-based active contour method is capable of classifying state space of particle filtering under the methodology of one class classification. By integrating this classifier into the particle filtering, geometric information introduced by the shape prior and pose invariance of the tracked object in the level set-based active contour method can be utilised to prevent the particles corresponding to outlier measurements from being heavily reweighted. Hence, this procedure reshapes and refines the posterior distribution of the particle filtering. To verify the performance of GATE, the performance of the standard particle filter is compared with that of GATE. Since video sequences in different applications are usually captured by diverse devices, GATE and the standard particle filters with the identical initialisation are studied on image sequences captured by the handhold, stationary and PTZ camera, respectively. According to experimental results, even though a simple color observation model based on the Hue-Saturation-Value (HSV) color histogram is adopted, the newly developed. GATE significantly improves the performance of the particle filtering for object tracking in complex environments. Meanwhile, GATE initialises a novel approach to tackle the impoverishment problem for recursive Bayesian estimation using sampling method.

Thesis (M.S.)--West Virginia University, 2008. / Title from document title page. Document formatted into pages; contains vii, 58 p. : ill. Includes abstract. Includes bibliographical references (p. 52-53).