Στη σημερινή εποχή, η πλειοψηφία των εφαρμογών που προορίζονται για επιτραπέζια υπολογιστικά συστήματα, ενσωματωμένα συστήματα και εξυπηρετητές, υλοποιείται χρησιμοποιώντας κάποια γλώσσα υψηλού επιπέδου. Το γεγονός αυτό αναδεικνύει την τεράστια σημασία των μεταγλωττιστών, οι οποίοι μεταφράζουν τον κώδικα υψηλού επιπέδου σε γλώσσα μηχανής. Η γνώση της τεχνολογίας των μεταγλωττιστών αποτελεί σημαντικό εφόδιο στην προσπάθεια αύξησης της απόδοσης ενός υπολογιστικού συστήματος. Σκοπός της παρούσας διπλωματικής εργασίας είναι η βελτιστοποίηση δύο γνωστών εφαρμογών, του μετασχηματισμού Gauss και του αλγορίθμου πολλαπλασιασμού μήτρας Toeplitz με διάνυσμα. Για τη βελτιστοποίηση χρησιμοποιήθηκε πληθώρα τεχνικών που ενσωματώνονται σε διάφορους μεταγλωττιστές, καθώς επίσης και μέθοδοι που οι τρέχοντες μεταγλωττιστές δεν μπορούν ακόμα να εφαρμόσουν. Για την αξιολόγηση των πειραματικών αποτελεσμάτων χρησιμοποιήθηκε το εργαλείο εξομοίωσης Simplescalar και πραγματοποιήθηκε σύγκριση της εκτέλεσης των αρχικών με τις βελτιστοποιημένες εκδόσεις των εφαρμογών. Η επιτάχυνση που επετεύχθη είναι σημαντική, έως και 55%. / Nowadays, the majority of applications designed for desktop and embedded systems and servers is implemented using a high level programming language. This fact proves the huge importance of compilers, which translate high level language into machine language. The knowledge of compiler technology is a useful tool for increasing efficiency of a computer system. The purpose of this Diploma Thesis is to optimize two well-known applications, the Gauss elimination algorithm and the algorithm for multiplying a Toeplitz matrix and a vector. In order to optimize these two algorithms, a variety of techniques present in many compilers was utilized, as well as techniques that current compilers cannot yet apply. For the evaluation of our technique we used Simplescalar simulator and we compared the results between the unoptimized and the optimized versions of the algorithms. The speedup achieved was very significant, up to 55%.

Embedded systems can be found everywhere in our daily lives. Due to the great variety of embedded devices, the platform independent Java language provides a good solution for embedded system development. Java virtual machine (JVM) is the most critical component of all kinds of Java platforms. Hence, it is extremely important to study the special design of JVM for embedded systems. The key challenges of designing a successful JVM for embedded systems are energy efficiency, time predictability and performance, which are investigated in this dissertation, respectively. We first study the energy issue of JVM on embedded systems. With a cycle-accurate simulator, we study each stage of Java execution separately to test the effects of different configurations in both software and hardware. After that, an alternative Adaptive Optimization System (AOS) model is introduced, which estimated the cost/benefit using energy data instead of running time. We tuned the parameters of this model to study how to improve the dynamic compilation and optimization in Jikes RVM in terms of energy consumption. In order to further reduce the energy dissipation of JVM on embedded systems, we study adaptive drowsy cache control for Java applications, where JVM can be used to make better decision on drowsy cache control. We explore the impact of different phases of Java applications on the timing behavior of cache usage. Then we propose several techniques to adaptively control drowsy cache to reduce energy consumption with minimal impact on performance. It is observed that traditional Java code generation and instruction fetch path are not efficient. So we study three hardware-based code caching strategies, which attempt to write and read the dynamically generated Java code faster and more energy-efficiently. Time predictability is another key challenge for JVM on embedded systems. So we exploit multicore computing to reduce the timing unpredictability caused by dynamic compilation and adaptive optimization. Our goal is to retain high performance comparable to that of traditional dynamic compilation and, at the same time, obtain better time predictability for JVM. We study pre-compilation techniques to utilize another core more efficiently. Furthermore, we develop Pre-optimization on Another Core (PoAC) scheme to replace AOS in Jikes JVM, which is very sensitive to execution time variation and impacts time predictability greatly. Finally, we propose two new approaches that automatically parallelizes Java programs at run-time, in order to meet the performance challenge of JVM on embedded systems. These approaches rely on run-time trace information collected during program execution, and dynamically recompiles Java byte code that can be executed in parallel. One approach utilizes trace information to improve traditional loop parallelization, and the other parallelizes traces instead of loop iterations.

The continued increasing use of microprocessors in embedded systems has caused a proliferation of embedded software in small devices. In practice, many of these devices are difficult to update to fix security flaws and software errors. This brings an emphasis on ensuring the secure and reliable software prior to the release of the device to ensure the optimal user experience. With the growing need to enable test and diagnostic capabilities into embedded devices the use of the JTAG interface has grown. While the intentions of the interface was originally to give the ability to shift in data into and out of chip’s scan chains for test, the generic framework has allowed for its features to expand. For embedded microprocessor’s the interface allows for halting execution, insertion of instructions, reprogramming the software, and reading from memory. While it creates a powerful debugging system, it also allows unlimited access to a malicious users. In turn such a user has the ability to either copy the intellectual property on the device, disable digital rights management routines, or alter the devices behavior. A novel method to secure JTAG access through the use of a multi-tiered permission system is presented in this paper. The use of static code analysis can be used to verify the functionality of embedded software code. Ideally, a software code should be tested in a way that guarantees correct behavior across all possible execution paths. While in practices this is typically infeasible due to the innumerable number of paths in the system, the use of automated test systems can help maximize the amount of code covered. In addition, such methods can also identify non-executable software statements that can be an indication of software issues, or sections of software that should not be targeted for testing. New static code analysis methods are presented in this dissertation. One technique uses supersets of software solution spaces to correctly identify unreachable software code in complex systems. Another presented technique automatically generates a set of test vectors to quickly maximize the number of code blocks executed by the set of test vectors. It is shown that such a method can be significantly faster than traditional methods.

Embedded devices constantly face two challenges in data security and energy efficiency. These devices are limited in processing such secure functions, as well as maintaining enough energy for the device to function properly. One example involves the healthcare industry, where some patients may require an Implantable Cardioverter Defibrillator (ICD) in their hearts to measure the heartbeat rate, while powered by a battery. The heartbeat rate is sent wirelessly, and the ICD can receive a jolt of electricity when the heartbeat rate reaches an abnormal value. Transmitting data alone, however, yields potential security risks when sending plain data. Work has shown that an attacker could intercept the heartbeat rate of the ICD, and intentionally send jolts of electricity. Also, replacing the battery on an ICD involves quite a painful process for the patient. A battery-less device that can receive energy wirelessly is much more convenient, but also poses a challenge where power loss may occur under long distances due to a limited supply of energy. In this paper, we design an adaptive light-weight scheduling mechanism that enhances data security, as well as improving energy efficiency on a device with such constraints. We will then prototype this scheduler on a Wireless Identification and Sensing Platform (WISP) device, which includes these constraints. Our results will then demonstrate the capabilities of such adaptive scheduling under various distances.

abstract: With the rise of the Internet of Things, embedded systems have become an integral part of life and can be found almost anywhere. Their prevalence and increased interconnectivity has made them a prime target for malicious attacks. Today, the vast majority of embedded devices are powered by ARM processors. To protect their processors from attacks, ARM introduced a hardware security extension known as TrustZone. It provides an isolated execution environment within the embedded device in which to deploy various memory integrity and malware detection tools. Even though Secure World can monitor the Normal World, attackers can attempt to bypass the security measures to retain control of a compromised system. CacheKit is a new type of rootkit that exploits such a vulnerability in the ARM architecture to hide in Normal World cache from memory introspection tools running in Secure World by exploiting cache locking mechanisms. If left unchecked, ARM processors that provide hardware assisted cache locking for performance and time-critical applications in real-time and embedded systems would be completely vulnerable to this undetectable and untraceable attack. Therefore, a new approach is needed to ensure the correct use of such mechanisms and prevent malicious code from being hidden in the cache. CacheLight is a lightweight approach that leverages the TrustZone and Virtualization extensions of the ARM architecture to allow the system to continue to securely provide these hardware facilities to users while preventing attackers from exploiting them. CacheLight restricts the ability to lock the cache to the Secure World of the processor such that the Normal World can still request certain memory to be locked into the cache by the secure operating system (OS) through a Secure Monitor Call (SMC). This grants the secure OS the power to verify and validate the information that will be locked in the requested cache way thereby ensuring that any data that remains in the cache will not be inconsistent with what exists in main memory for inspection. Malicious attempts to hide data can be prevented and recovered for analysis while legitimate requests can still generate valid entries in the cache. / Dissertation/Thesis / Masters Thesis Computer Science 2018

abstract: Majority of the Sensor networks consist of low-cost autonomously powered devices, and are used to collect data in physical world. Today's sensor network deployments are mostly application specific & owned by a particular entity. Because of this application specific nature & the ownership boundaries, this modus operandi hinders large scale sensing & overall network operational capacity. The main goal of this research work is to create a mechanism to dynamically form personal area networks based on mote class devices spanning ownership boundaries. When coupled with an overlay based control system, this architecture can be conveniently used by a remote client to dynamically create sensor networks (personal area network based) even when the client does not own a network. The nodes here are "borrowed" from existing host networks & the application related to the newly formed network will co-exist with the native applications thanks to concurrency. The result allows users to embed a single collection tree onto spatially distant networks as if they were within communication range. This implementation consists of core operating system & various other external components that support injection maintenance & dissolution sensor network applications at client's request. A large object data dissemination protocol was designed for reliable application injection. The ability of this system to remotely reconfigure a network is useful given the high failure rate of real-world sensor network deployments. Collaborative sensing, various physical phenomenon monitoring also be considered as applications of this architecture. / Dissertation/Thesis / M.S. Computer Science 2013

The goal of the master thesis is to investigate the feasibility ofhaving distributed machine learning on embedded devices and toanalyse how the architecture of such a system can look like. A systemis proposed which enables machine learning running on multipleembedded devices to communicate with an end application. Theapplication communicates with the distributed machine learning via agateway, which decouples the application. The proposed system isimplemented as a proof of concept system, which utilizes distributedmachine learning to achieve gesture recognition. The Intel Curiemodule was selected as the embedded device, as it provides a hardwareaccelerated implementation of the machine learning algorithmsK-Nearest Neighbour and Radial Basis Function. This module alsoprovides accelerometer/gyroscope sensors for collecting gesture dataas well as Bluetooth Low Energy, which enables wireless communicationwith other devices. The implemented system shows that it is feasibleto implement distributed machine learning on embedded devices if themachine learning is hardware accelerated. If a hardware acceleratorwas not used the computational load on the embedded device willincrease, which will increase the overall power consumption. For alow powered and constrained devices, hardware accelerated machinelearning is likely the best approach to implement edge intelligence.

Developing software is both time consuming and expensive. Finding waysfor minimizing development cost is therefore of great interest. One way ofreducing cost in software development is reuse of existing software. Portingsoftware is a type of reuse where an existing piece of software is adapted torun in a di erent environment than originally intended. Successfully portingsoftware requires both good preparations and evaluation of results. Guide-lines for this process are provided in this thesis. In this thesis an existingembedded software platform for automotive telematics was partially portedto a new type of hardware.

Unique customizations (options) of features in forklifts are often requested by customers. When new options are created or existing options have to be modified in the main software the complexity increases, the firmware revision pool gets large and with the increasing code size the memory limit is threatened. This affects the software development since the frequent modification of the option handler software is very resource consuming. Therefore it is desirable to have a highly modular system for the option handler to simplify the development process. Although the market value of this improvement is negligible the possible long term savings is the desirable effect. This thesis explores the possibility of migrating the option handling software to a dedicated hardware module. This helps the development process by increasing the modularity of the system architecture and thus reducing the development scope. The tools and the approach to accomplish this option handler is analyzed. A system model of the resulting approach is designed and a prototype is developed to validate the result.

Ericsson has always strived for the technology leadership in its offering by designing products based on the latest technology. Going ahead with a similar thought it started exploring an idea of running a mobile core application using a Simplified Infrastructure (SI) to eventually enable the Cloud based solutions. But in order to run these type of applications in the Cloud, the in-service performance provided by such a SI should be the same as the native infrastructure in order to maintain the mobile core application’s QoS. "High availability" of the infrastructure is one of the measure of the ISP and from the ISP point of view, such a migration would be considered feasible only if the SI is able to maintain the same level of availability as provided by the native infrastructure solution without bringing in any major architecture changes within the SI. Hence this master thesis project investigates the feasibility of achieving the same availability as before if the mobile core application is to be migrated from the native infrastructure to the SI. Such a feasibility exploration was the very first attempt with respect to the SI within Ericsson, which was executed through this master thesis project. In order to achieve the goal of this thesis project a detailed system study was carried out, which focused on the native infrastructure architecture, how it was maintaining the "high availability" and how it differed from the SI. In the end, it was possible to confirm that the level of availability of infrastructure services as provided through the SI will be higher than the native infrastructure after the migration if the proposed suggestions of this master thesis project are implemented successfully. These implementations also do not change the architecture of the SI in any major way. The end results of this thesis project were also highly appreciated by Ericsson and are now part of thedevelopment plan for next mobile core infrastructure solution at Ericsson.