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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
281

Simulation Framework of embedded systems in armored vehicle design / Simuleringsramverk av inbyggda system i bandvagnsdesign

Bergström, Christoffer January 2021 (has links)
Embedded systems are a mixture of electric and mechanical hardware along with the software that is controlling them. BAE Systems Hägglunds, which designs and builds armored vehicles, is interested in knowing how to simulate these systems for logic validation and testing different design variations.  The goal of this thesis was to create a framework for carrying out these simulations. This was done by analyzing hardware and software design at BAE and Identifying the necessary conditions for creating a model which can be simulated.  Matlab Simulink is suggested as the tool for these simulations. The framework suggests dividing the model into smaller modules which reflects design principles at BAE. These modules will be made up of sub-modules containing hardware and software in layers. The hardware foundation will be made up of pre-designed components created in Simulink’s physical simulation library. The software will be imported into specialized sub-modules and integrated into the hardware using proposed bridge functions, converting information between the two systems. The framework is designed to provide a comprehensive solution instead of a deep one that can be adapted to changing circumstances. Tests have been made on small-scale systems, but the framework still needs to be tested on a large-scale system, which was not possible during this thesis. In conclusion, this is a stable foundation that needs to be built upon.
282

Optimal Bond Refunding: Evidence From the Municipal Bond Market

Priyadarshi, Samaresh 05 September 1997 (has links)
This dissertation empirically examines refunding decisions employed by issuers of tax-exempt bonds. Callable bonds contain embedded call options by virtue of provisions in bond indentures that permit the issuing firm to buy back the bond at a predetermined strike price. Such an embedded American call option has two components to its value, the intrinsic value and the time value. The issuer can realize at least as much as the intrinsic value by exercising immediately, when the option is in-the-money. Usually it is optimal for the holder of an in-the money American option to wait rather than exercise immediately, because the option has time value. It is rational for the holder to exercise the option when the total value of the option is no more than the intrinsic value. Option pricing theory can be used to identify two sub-optimal refunding strategies: those that refund too early, and those that refund too late. In such cases the holder incurs losses. I analyze the refunding decisions for two different samples of tax-exempt bonds issued between 1986 and 1993: the first consists of 2,620 bonds that are called, and the second contains 23,976 bonds that are never called. The generalized Vasicek (1977) model in the Heath, Jarrow, and Morton (1992) framework is used to construct binomial trees for interest rates, bond prices, and call option prices. The option pricing lattice is then used to compute the loss in value from sub-optimal refunding strategies, refunding efficiency, and months from optimal time for bonds in these two samples. Results suggest that sub-optimal refunding decisions cause losses to the issuers, which are present across bond and issuer characteristics. For the pooled sample of 26,596 bonds, the loss in value from sub-optimal refunding decisions totaled $7.2 billion, amounting to a loss of about 1.75% of total principal amount. Results indicate that issuers either wait too long to refund or never refund and cannot realize the present value saving of switching a high coupon bond with a low coupon bond, over a longer period of time. These results critically depend on the assumptions of underlying term structure model and are sensitive to model calibrated parameter values. / Ph. D.
283

Ingénierie des exigences pour la conception d'architectures de sécurité de systèmes embarqués distribués / A requirement engineering driven approach to security architecture design for distributed embedded systems

Idrees, Muhammad Sabir 21 September 2012 (has links)
Au cours des dix dernières années, l’impact des questions de sécurité sur le développement et la mise en oeuvre des systèmes embarqués distribués n’a jamais cessé de croître. Ceci est principalement lié à l’interconnexion toujours plus importante de ces systèmes qui les rend vulnérables aux attaques, ainsi qu’à l’intérêt économique d’attaquer ces systèmes qui s’est simultanément accru. Dans un tel contexte, méthodologies et outils d’ingénierie des exigences de sécurité sont devenus indispensables pour prendre des décisions appropriées quant a` la sécurité, et ce le plus tôt possible. L’ingénierie des exigences devrait donc fournir une aide substantielle à l’explicitation et à la spécification des problèmes et solutions de sécurité des logiciels bien avant que concepteurs et développeurs ne soient engagés dans une implantation en particulier. Toutefois, et c’est particulièrement vrai dans les systèmes embarqués, les exigences de sécurité ne doivent pas être considérées seulement comme l’expression abstraite d’un ensemble de propriétés indépendamment de l’architecture système ou des menaces et des attaques qui pourraient y survenir. Nous estimons que cette considération est d’une importance capitale pour faire de l’ingénierie des exigences un guide et un moteur de la conception et de la mise en œuvre d’un système sécurisé. Notre approche s’appuie en particulier sur une approche centrée sur les connaissances de l’ingénierie des exigences de sécurité, applicable dès les premières phases de conception du système jusqu’à la mise en application des exigences de sécurité dans l’implantation. / During the last ten years, the impact of security concerns on the development and exploration of distributed embedded systems never ceased to grow. This is mainly related to the fact that these systems are increasingly interconnected and thus vulnerable to attacks, and that the economic interest in attacking them has simultane- ously increased. In such a context, requirement engineering methodologies and tools have become necessary to take appropriate decisions regarding security early on. Security requirements engineering should thus strongly support the elicitation and specifica- tion of software security issues and solutions well before designers and developers are committed to a particular implementation. However, and that is especially true in embedded systems, security requirements should not be considered only as the abstract expression of a set of properties independently from the system architecture or from the threats and attacks that may occur. We believe this consideration is of utmost importance for security requirements engineering to be the driving force behind the design and implementation of a secure system. We thus describe in this thesis a security engineering requirement methodology depending upon a constant dialog between the design of system functions, the requirements that are attached to them, the design and development of the system architecture, and the assessment of the threats to system assets. Our approach in particular relies on a knowledge-centric approach to security requirement engineering, applicable from the early phases of system conceptualization to the enforcement of security requirements.
284

Embedded and Unilateral Journalists: How their Access to Sources Affected their Framing During the 2003 Iraq War

Huck, Courtney January 2017 (has links)
No description available.
285

RVSingle: A general purpose power efficient RISC-V for FPGAs

Shen, YuYang January 2023 (has links)
With the increasing need for low-cost, power-efficient computing units, RISC-Vas an open-standard Instruction Set Architecture (ISA) is becoming more and more popular in the industry. There are multiple open-source RISC-V soft processors like cva6, VEGA, NOEL-V and more. But those processors have a common problem in that they can only be implemented onto a specific FPGA development platform. This thesis introduces a new processor design with compatibility in mind so that it will not be limited to a certain development platform but can be used on multiple different platforms as far as they meet the basic requirements. This processor is a single-stage processor without any pipeline implemented. The processor is used to evaluate the power efficiency of the architecture and has a unique feature to enable or disable the RISC-V Compressed (RVC) instruction subset to understand its impact on power-efficient. It is simple in architecture but still has the full capability for the RV64IC instruction set. Because of it uses RISC-V architecture, in the future, this processor can be easily expanded to adopt more RISC-V instruction subsets.
286

Improving Throughput and Predictability of High-volume Business Processes Through Embedded Modeling

DeKeyrel, Joseph S. 01 January 2011 (has links)
Being faster is good. Being predictable is better. A faithful model of a system, loaded to reflect the system's current state, can then be used to look into the future and predict performance. Building faithful models of processes with high degrees of uncertainty can be very challenging, especially where this uncertainty exists in terms of processing times, queuing behavior and re-work rates. Within the context of an electronic, multi-tiered workflow management system (WFMS) the author builds such a model to endogenously quote due dates. A WFMS that manages business objects can be recast as a flexible flow shop in which the stations that a job (representing the business object) passes through are known and the jobs in the stations queues at any point are known. All of the other parameters associated with the flow shop, including job processing times per station, and station queuing behavior are uncertain though there is a significant body of past performance data that might be brought to bear. The objective, in this environment, is to meet the delivery date promised when the job is accepted. To attack the problem the author develops a novel heuristic algorithm for decomposing the WFMS's event logs exposing non-standard queuing behavior, develops a new simulation component to implement that behavior, and assembles a prototypical system to automate the required historical analysis and allow for on-demand due date quoting through the use of embedded discrete event simulation modeling. To attack the problem the author develops a novel heuristic algorithm for decomposing the WFMS's event logs exposing non-standard queuing behavior, develops a new simulation component to implement that behavior, and assembles a prototypical system to automate the required historical analysis and allow for on-demand due date quoting through the use of embedded discrete event simulation modeling. The developed software components are flexible enough to allow for both the analysis of past performance in conjunction with the WFMS's event logs, and on-demand analysis of new jobs entering the system. Using the proportion of jobs completed within the predicted interval as the measure of effectiveness, the author validates the performance of the system over six months of historical data and during live operations with both samples achieving the 90% service level targeted.
287

The Development Of A Dismounted Infantry Embedded Trainer With An Intelligent Tutor System

Sims, Jason 01 January 2006 (has links)
The dismounted infantry system is a man wearable system with intelligent tutoring tool used to assess training. The tasks used to assess training for the intelligent tutoring were: (1) move as a member of a fireteam, (2) enter and clear a room, and (3) report battlefield information. The soldier wearing the simulation system acts as a member of a fireteam to conduct a virtual mission. The soldier's teammates are computer generated entities to conduct the mission. Soldiers were surveyed on the tasks assessed as well as the features of the system. Soldiers were also surveyed on tasks they felt needed to be added to the tutoring functions of the system. The intelligent tutor system and training in virtual reality was generally accepted by the participants. The general consensus was the technology needed additional refinement to provide a better training environment. Most felt that working with Semi-Automated Forces (SAF) entities made the scenario more difficult to execute. The parameters established for successful completion of the movement and reporting tasks were too strict and hindered the experience for the participant. Locomotion is another aspect that deserves further research. Moving the locomotion controls to the feet would free the soldier from having to accomplish multiple tasks with only two hands. Future research should concentrate on locomotion methods and controls, as well as only using human participants for all unit members.
288

Using HLS for Acceleration of FPGA Development: A 3780-Point FFT Case Study

Hejdström, Christoffer January 2022 (has links)
Manually designing hardware for fpga implementations is time consuming. Onepossible way to accelerate the development of hardware is to use high level syn-thesis (hls) tools. Such tools synthesizes a high level model written in a languagesuch as c++ into hardware. This thesis investigates hls and the efficacy of using hls in the hardware design flow. A 3780-point fast Fourier transform optimized for area is used to compare Vitis hls with a manual hardware implementation. Different ways of writing the highlevel model used in hls and their impacts in the synthesized hardware together with other optimizations is investigated. This thesis concludes that the results from the hls implementation are not comparable with the manual implementation, they are significantly worse. Further, high level code written from a non-hardware point of view needs to be rewritten from a hardware point of view to provide good results. The use of high level synthesis is not best used by designers from an algorithm or software background, but rather another tool for hardware designers. High level synthesis can be used as an initial design tool, allowing for quick exploration of different designs andarchitectures.
289

DDoS Defense: Next-Generation Firewall versus Traditional Firewall / DDoS Defense: Next-Generation Firewall versus Traditional Firewall

Andell, William, Eskel, Filip January 2023 (has links)
Syftet med detta examensarbete var att utvärdera hur två olika brandväggar, en nästa generationens brandvägg och en traditionell brandvägg, hanterade en mindre distribuerad denial of service-attack. Enheterna kördes så nära dess förkonfiguration som möjligt. Testningengenomfördes i en kontrollerad labbmiljö på Högskolan Väst. Ett botnät bestående av 17 datorer användes och styrdes via en kommandocentral som använde IRC för att utföra attackerna. Enheterna testades med TCP- och UDP-baserade attacker under en tid av fyra minuter vardera. En dator var ansluten till det interna gränssnittet där vi kontrollerade minnet, CPU och latensen. En annan dator från botnätgränssnittet kontrollerade latensen från botnät. Resultaten visar att nästa generationens brandvägg (FortiGate40F) presterar bättre än den traditionell brandväggen (ASA 5506-X). Både Cisco ASA 5506-X och FortiGate 40F kör med 4 CPU-kärnor, där ASA 5506-X har 1250 MHz per kärna medan FortiGate 40F bara har 1200M MHz per kärna. ASA 5506-X har också 113,24% mer RAM än FortiGate. Trots att ASA 5506-X har fördelen när det gäller hårdvara, presterande FortiGate 40F bättre vid varje attack. Detta beror med stor sannolikhet på skillnaden i mjukvara hos de olika brandväggar
290

Buffer Overflow Attack and Prevention for Embedded Systems

Sikiligiri, Amjad Basha M. 26 September 2011 (has links)
No description available.

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