Kiekvienas, kuris kuria aparatūrinę įrangą, nori, tai atlikti kiek įmanoma greičiau ir už kuo mažesnius kaštus. Gaminys turi greitai patekti į rinką, nes egzistuojanti konkurencija yra labai didelė. Tai galima padaryti naudojant specialią programinę įrangą, vadinamus aukšto lygio sintezės įrankius. HLS įrankiai automatiškai generuoja HDL RTL aprašą bei padeda projektuotojams turėti visas galimas projekto architektūras. HLS įrankiai naudoja algoritminį C aprašą kaip įvesties duomenis. Čia atsiranda galimybė PĮ inžinieriams taip pat projektuoti aparatūrinę įrangą. Nors atrodo, jog HLS technologija yra labai gera, bet šie įrankiai šiandien plačiai nėra naudojami. Turi būti surasti problemu sprendimai. Šioms problemoms spręsti atliekamas eksperimentas. GSM LPC algoritmas rankiniu būdu perrašomas iš C kalbos aprašo į VHDL RTL. Eksperimentas paaiškina aukšto lygio sintezės problemas. Norint, kad HLS įrankiai būtų plačiai naudojami, aukšto abstrakcijos lygio C/C++ aprašas turi būti rašomas su atitinkamais apribojimais. Neturi būti naudajami rodyklės tipo kintamieji, rodyklės tipo kintamųjų aritmetikos, rekursijos, sudėtingų operacijų, dinaminio atminties rezervavimo. Projektuotojai turi mąstyti taip kaip aparatūrinė įranga. / Everyone who develops hardware wants to do this as fast as possible and for low costs. Time to the market must be shortened because the competition is very substantial. This can be done by using special development software called high level synthesis tools. HLS tools automatically generate HDL RTL code and helps developers to get all possible architectures of project. HLS tools use an algorithmic C code as input information. There is the possibility for software engineers to develop hardware too. It seems that HLS is very good technology, but HLS tools are not widely used today. It must be found the reasons of this problem and opportunities how this problem can be solved. An experiment is made by solving this problem. A GSM LPC algorithm is written by hand from C description to VHDL RTL. This experiment explains problems of high level synthesis. With the purpose HLS tools to use widely, high level of abstraction (C/C++) code must be written with restrictions. There must be no pointer variables and pointer arithmetic, no recursion, no difficult operations, no dynamic memory allocation. Engineers have to think like hardware.

Whether it's capturing a car's license plate on the highway or detecting someone's facial features to tag friends, computer vision and image processing have found their way into many facets of our lives. Image and video processing algorithms ultimately tailor towards one of two goals: to analyze data and produce output in as close to real-time as possible, or to take in and operate on large swaths of information offline. Image convolution is a mathematical method with which we can filter an image to highlight or make clearer desired information. The most popular uses of image convolution accentuate edges, corners, and facial features for analysis. The goal of this project was to investigate various image convolution algorithms and compare them in terms of hardware usage, power utilization, and ability to handle substantial amounts of data in a reasonable amount of time. The algorithms were designed, simulated, and synthesized for the Zynq-7000 FPGA, selected both for its flexibility and low power consumption.

abstract: Video capture, storage, and distribution in wireless video sensor networks (WVSNs) critically depends on the resources of the nodes forming the sensor networks. In the era of big data, Internet of Things (IoT), and distributed demand and solutions, there is a need for multi-dimensional data to be part of the Sensor Network data that is easily accessible and consumable by humanity as well as machinery. Images and video are expected to become as ubiquitous as is the scalar data in traditional sensor networks. The inception of video-streaming over the Internet, heralded a relentless research for effective ways of distributing video in a scalable and cost effective way. There has been novel implementation attempts across several network layers. Due to the inherent complications of backward compatibility and need for standardization across network layers, there has been a refocused attention to address most of the video distribution over the application layer. As a result, a few video streaming solutions over the Hypertext Transfer Protocol (HTTP) have been proposed. Most notable are Apple’s HTTP Live Streaming (HLS) and the Motion Picture Experts Groups Dynamic Adaptive Streaming over HTTP (MPEG-DASH). These frameworks, do not address the typical and future WVSN use cases. A highly flexible Wireless Video Sensor Network Platform and compatible DASH (WVSNP-DASH) are introduced. The platform's goal is to usher video as a data element that can be integrated into traditional and non-Internet networks. A low cost, scalable node is built from the ground up to be fully compatible with the Internet of Things Machine to Machine (M2M) concept, as well as the ability to be easily re-targeted to new applications in a short time. Flexi-WVSNP design includes a multi-radio node, a middle-ware for sensor operation and communication, a cross platform client facing data retriever/player framework, scalable security as well as a cohesive but decoupled hardware and software design. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

Manually designing hardware for fpga implementations is time consuming. Onepossible way to accelerate the development of hardware is to use high level syn-thesis (hls) tools. Such tools synthesizes a high level model written in a languagesuch as c++ into hardware. This thesis investigates hls and the efficacy of using hls in the hardware design flow. A 3780-point fast Fourier transform optimized for area is used to compare Vitis hls with a manual hardware implementation. Different ways of writing the highlevel model used in hls and their impacts in the synthesized hardware together with other optimizations is investigated. This thesis concludes that the results from the hls implementation are not comparable with the manual implementation, they are significantly worse. Further, high level code written from a non-hardware point of view needs to be rewritten from a hardware point of view to provide good results. The use of high level synthesis is not best used by designers from an algorithm or software background, but rather another tool for hardware designers. High level synthesis can be used as an initial design tool, allowing for quick exploration of different designs andarchitectures.

While Field-Programmable Gate Arrays (FPGAs) exist in many design configurations throughout the data center, cloud, and edge, the promise of performance and flexibility offered by the FPGA often remains unrealized for lack of hardware design expertise, with most computation remaining in fixed hardware such as CPUs, GPUs, and ASICs e.g. tensor processors. Identifying programmability as a barrier to FPGA usage, we seek to augment High Level Synthesis (HLS) design flows with machine learning. The overall goal of this dissertation is to advance the art of using unmodified high-level language (HLL) programs to create FPGA configurations that are performant, programmable, and portable. The problems in using HLL code to program FPGAs arise from the serial execution model of the target application codes, in particular, the mismatch between that model and the arbitrary data flow model of the target hardware. However, a variety of code transformation techniques, tedious to perform by a human but readily and effortlessly done by CPU compilers, allow many compute-intensive operations to be transformed into a form that is highly or massively parallel. A challenge then exists in selecting the best set of optimizations and an order in which to perform them, a choice among staggeringly many options. Brute-force and automated orthogonal search techniques have failed to produce solutions that lie within the realm of practicality. We evaluate the suitability of machine learning (ML) models to address this challenge. We develop and assess designs for systems that use ML and present feedback to these models based on their recommendations. In support of using ML models, we begin by developing and assessing methods for preparing the original program as input for processing by the model. We next develop and assess methods to apply the model's output to a compilation system and evaluate the results for use as feedback. Machine learning experiments are performed to demonstrate their potential. Feasibility is studied through simulations and specialized evaluation techniques as appropriate. Specific new artifacts are created, including extensions to the open-source GCC compiler. The significance of this work is of several types: the many options and variants to the overall design that are considered, with their distinct advantages and disadvantages; the application of proper units and baselines to experimental measurements; and the numerous contributions in the form of published extensions and improvements to open-source projects.

Considerando a crescente demanda por desempenho em sistemas computacionais, a implementação de algoritmos diretamente em hardware com o uso de FPGAs (Field-programmable Gate Arrays) é uma alternativa que tem apresentado bons resultados. Porém, os desafios de programação envolvidos no uso de FPGAs, de tal forma a explorar eficientemente seus recursos, limita o número de desenvolvedores em função da predominância do paradigma de programação tradicionalmente sequencial, imposto pelas linguagens imperativas. Assim, este trabalho busca desenvolver mecanismos que facilitem o desenvolvimento com FPGAs, otimizando o uso de memória e explorando o paralelismo das operações. Este documento apresenta a tese de doutorado de título LALP+ : um framework para o desenvolvimento de aceleradores de hardware em FPGAs. Dado que a latência para leitura e escrita de dados têm sido um gargalo para algumas aplicações de alto desempenho, este trabalho trata do desenvolvimento de técnicas para geração de arquiteturas de hardware, considerando aspectos relativos ao mapeamento, gerenciamento e acesso à memória em arquiteturas reconfiguráveis. Para isto, o projeto desenvolvido utiliza como base a linguagem LALP, cujo foco é o tratamento de loops com a técnica de loop pipelining. As técnicas descritas nesta tese são empregadas no desenvolvimento do framework LALP+, o qual estende LALP com a implementação de novas características e funcionalidades, de forma a contribuir para o aumento do seu nível de abstração. As arquiteturas criadas utilizando LALP+ foram comparadas às geradas por ferramentas comerciais e acadêmicas, tendo apresentado, em média, um melhor desempenho, com redução do tempo de execução de 10;01, no melhor caso. Espera-se, por meio das contribuições aqui apresentadas, facilitar a implementação de produtos e projetos relacionados a aplicações de computação de alto desempenho que envolvam o uso de arquiteturas reconfiguráveis, promovendo uma maior absorção desta tecnologia. / Considering the demand for high-performance in computer systems, the implementation of algorithms directly in hardware by using FPGAs (Field-programmable Gate Arrays) is an alternative that has shown good results. However, the number of developers is limited due to the challenges faced for efficiently programming FPGAs. In addition to that, developers are more used to the traditional sequential programming paradigm imposed by the imperative languages. This work seeks to develop mechanisms to facilitate the development with FPGAs, by optimizing memory usage and exploiting the parallelism of operations inside a loop. This document presents the doctoral thesis entitled LALP+ : a framework for developing FPGA-based hardware accelerators. Since the latency for reading and writing data have been a bottleneck for high performance applications, this work deals with the development of techniques for generation of hardware architectures, considering aspects related to mapping, management and memory access in reconfigurable architectures, using as basis the LALP language, which focuses on the treatment of loops with the technique of loop pipelining. The techniques described in this thesis are employed in the development of the LALP+ framework, which extends LALP by implementing new features and functionalities, in order to contribute to increase its abstraction level. LALP+ architectures were compared to ones generated by using academical and commercial tools, having presented, on average, better performance, with a execution time speedup of 10;01 for the best case. Thus, it is expected that the hereby presented contributions facilitate the implementation of products and projects related to high-performance computing applications with reconfigurable architectures, contributing for the use of such technology.

Les réseaux sur puce (NoC pour «network on chip») sont des infrastructures de communication extensibles qui autorisent le parallélisme dans la communication. La conception de circuits basés sur les NoC se fait en considérant la communication et le calcul séparément, ce qui la rend plus complexe. Les outils de synthèse d'architecture (HLS pour «high level synthesis») permettent de générer rapidement des circuits performants. Mais le contrôle de ces circuits est centralisé et la communication est de type point-à-point (non extensible). Afin d'exploiter le parallélisme potentiel des algorithmes sur des FPGA dont les ressources augmentent constamment, les outils de HLS doivent extraire le parallélisme d'un programme et utiliser les ressources disponibles de manière optimisée. Si certains outils de synthèse considèrent une spécification de type flot de données, la plupart de concepteurs d'algorithmes utilise des programmes pour spécifier leurs algorithmes. Mais cette représentation comportementale doit souvent être enrichie d'annotations architecturales afin de produire en sortie un circuit optimisé. De plus, une solution complète d'accélération nécessite une intégration du circuit dans un environnement de développement, comme les GPU aujourd'hui. Un frein à l'adoption des FPGA et plus généralement des architectures parallèles, est la nécessaire connaissance des architectures matérielles ciblées.Dans cette thèse, nous présentons une méthode de synthèse qui utilise une technique d'analyse symbolique pour extraire le parallélisme d'une spécification algorithmique écrite dans un langage de haut niveau. Cette méthode introduit la synthèse de NoC pendant la synthèse d'architecture. Afin de dimensionner le circuit final, une modélisation mathématique du NoC est proposée afin d'estimer la consommation en ressources du circuit final. L'architecture générée est extensible et de type flot de données. Mais l'atout principal de l'architecture générée est son aspect programmable car elle permet, dans une certaine mesure, d'éviter les synthèses logiques pour modifier l'application / Network-on-Chip (NoC) introduces parallelism in communications and emerges with the growing integration of circuits as large designs need scalable communication architectures. This introduces the separation between communication tasks and processing tasks, and makes the design with NoC more complex. High level synthesis (HLS) tools can help designers to quickly generate high quality HDL (Hardware Description Level) designs. But their control schemes are centralized, usually using finite state machines. To take benefit from parallel algorithms and the ever growing FPGAs, HLS tools must properly extract the parallelism from the input representation and use the available resources efficiently. Algorithm designers are used with programming languages. This behavioral specification has to be enriched with architectural details for a correct optimization of the generated design. The C to FPGA path is not straightforward, and the need for architectural knowledges limits the adoption of FPGAs, and more generally, parallel architecture. In this thesis, we present a method that uses a symbolic analysis technique to extract the parallelism of an algorithmic specification written in a high level language. Parallelization skills are not required from the users. A methodology is then proposed for adding NoCs in the automatic design generation that takes the benefit of potential parallelizations. To dimension the design, we estimate the design resource consumption using a mathematical model for the NoC. A scalable application, hardware specific, is then generated using a High Level Synthesis flow. We provide a distributed mechanism for data path reconfiguration that allows different applications to run on the same set of processing elements. Thus, the output design is programmable and has a processor-less distributed control. This approach of using NoCs enables us to automatically design generic architectures that can be used on FPGA servers for High Performance Reconfigurable Computing. The generated design is programmable. This enable users to avoid the logic synthesis step when modifying the algorithm if a existing design provide the needed operators

Considerando a crescente demanda por desempenho em sistemas computacionais, a implementação de algoritmos diretamente em hardware com o uso de FPGAs (Field-programmable Gate Arrays) é uma alternativa que tem apresentado bons resultados. Porém, os desafios de programação envolvidos no uso de FPGAs, de tal forma a explorar eficientemente seus recursos, limita o número de desenvolvedores em função da predominância do paradigma de programação tradicionalmente sequencial, imposto pelas linguagens imperativas. Assim, este trabalho busca desenvolver mecanismos que facilitem o desenvolvimento com FPGAs, otimizando o uso de memória e explorando o paralelismo das operações. Este documento apresenta a tese de doutorado de título LALP+ : um framework para o desenvolvimento de aceleradores de hardware em FPGAs. Dado que a latência para leitura e escrita de dados têm sido um gargalo para algumas aplicações de alto desempenho, este trabalho trata do desenvolvimento de técnicas para geração de arquiteturas de hardware, considerando aspectos relativos ao mapeamento, gerenciamento e acesso à memória em arquiteturas reconfiguráveis. Para isto, o projeto desenvolvido utiliza como base a linguagem LALP, cujo foco é o tratamento de loops com a técnica de loop pipelining. As técnicas descritas nesta tese são empregadas no desenvolvimento do framework LALP+, o qual estende LALP com a implementação de novas características e funcionalidades, de forma a contribuir para o aumento do seu nível de abstração. As arquiteturas criadas utilizando LALP+ foram comparadas às geradas por ferramentas comerciais e acadêmicas, tendo apresentado, em média, um melhor desempenho, com redução do tempo de execução de 10;01, no melhor caso. Espera-se, por meio das contribuições aqui apresentadas, facilitar a implementação de produtos e projetos relacionados a aplicações de computação de alto desempenho que envolvam o uso de arquiteturas reconfiguráveis, promovendo uma maior absorção desta tecnologia. / Considering the demand for high-performance in computer systems, the implementation of algorithms directly in hardware by using FPGAs (Field-programmable Gate Arrays) is an alternative that has shown good results. However, the number of developers is limited due to the challenges faced for efficiently programming FPGAs. In addition to that, developers are more used to the traditional sequential programming paradigm imposed by the imperative languages. This work seeks to develop mechanisms to facilitate the development with FPGAs, by optimizing memory usage and exploiting the parallelism of operations inside a loop. This document presents the doctoral thesis entitled LALP+ : a framework for developing FPGA-based hardware accelerators. Since the latency for reading and writing data have been a bottleneck for high performance applications, this work deals with the development of techniques for generation of hardware architectures, considering aspects related to mapping, management and memory access in reconfigurable architectures, using as basis the LALP language, which focuses on the treatment of loops with the technique of loop pipelining. The techniques described in this thesis are employed in the development of the LALP+ framework, which extends LALP by implementing new features and functionalities, in order to contribute to increase its abstraction level. LALP+ architectures were compared to ones generated by using academical and commercial tools, having presented, on average, better performance, with a execution time speedup of 10;01 for the best case. Thus, it is expected that the hereby presented contributions facilitate the implementation of products and projects related to high-performance computing applications with reconfigurable architectures, contributing for the use of such technology.

This diploma thesis focuses on the High-level synthesis (HLS). The first part deals with theoretical details and methods that are used in HLS tools. This is followed by a description of the synthesis tool Vivado HLS which will be used for implementation of an application. In the second part is briefly introduced high dynamic range images (HDR) and tone mapping. The third part is dedicated to design and implementation of the aplication which implements tone mapping methods in HDR images. This methods are implemented in Vivado HLS and language C++. This application is based on platform Xilinx Zynq and it uses multiexposure camera for capturing HDR images. Images are transmitted to FPGA for tone mapping processing.

A floresta ombrófila mista, representada principalmente pela presença de Araucaria angustifolia possui elevada importância para a região sul do Brasil e o interesse econômico nessa espécie ocasionou uma forte exploração principalmente durante a primeira metade do século XX. O Parque Nacional das Araucárias possui a finalidade de preservar remanescentes de florestas com a presença de Araucaria angustifolia; sendo assim, a compreensão do comportamento da dinâmica fenológica das coberturas florestais é uma forma de auxiliar na gestão e manejo destas áreas. Dessa forma, foi executado a aplicação de uma metodologia baseada em análises harmônicas de séries temporais EVI/MODIS para realizar a caracterização e mapeamento fenológico das diferentes coberturas vegetais presentes no Parque Nacional das Araucárias, por meio desta metodologia foi possível identificar os valores médios de EVI durante toda a série temporal para as diferentes coberturas de uso e ocupação do solo, analisando a relação entre as variações fenológicas com dados de precipitação e temperatura máxima, representando essas variações de amplitude, fase e termo aditivo para a série completa e individualmente para cada ano. Baseado no algoritmo HANTS, aplicou-se a análise harmônica para uma série temporal de dez anos, compreendidas entre os anos de 2006 a 2015. A partir desse processamento foram analisadas as imagens de fase, amplitude e termo aditivo por meio de quatro conjunto de amostras previamente selecionadas, representando as quatro principais coberturas de vegetação presentes no parque. Com o intuito de auxiliar na interpretação visual dos dados, as imagens foram convertidas de RGB para HLS. Uma vez gerados todos os dados, foi possível caracterizar como ocorre a variação dos valores de índices de vegetação ao longo do ano, bem como o período do ano onde acontecem as maiores variações; além de ser possível indicar as áreas onde houve indicativos de mudanças significativas de uso do solo, mudanças ocasionadas por algum evento climático ou pelo próprio desenvolvimento da vegetação. Através dos dados extraídos com a análise harmônica e a identificação das diferentes fenologias gerou-se também uma classificação sobre a série temporal, com o objetivo de identificar as áreas que ainda apresentam remanescentes de Araucaria angustifolia de forma predominante. Por fim, concluiu-se que a aplicação de uma metodologia baseada em séries harmônicas possibilita uma maior compreensão das coberturas florestais presentes nesta unidade de conservação gerando informações úteis para a gestão e possível revisão do plano de manejo. Para alguma aplicação futura, espera-se utilizar esta metodologia em uma série temporal com maior resolução espacial. / The Mixed Coniferous-Broadleaf forest, mainly represented by the presence of Araucaria angustifolia, is highly important to the southern region of Brazil, the economic interest in this species led to a heavy exploration during the first half of the 20th century. The purpose of the Araucárias National Park is to preserve remnants of the forests with great presence of Araucaria angustifolia; therefore, the comprehension of the behavior of the phenological dynamic of the forest covers is a way of assisting the management and handling of these areas. Thereby, the goal is to apply a methodology based on harmonic analysis of EVI / MODIS time series to perform characterization and phenological mapping of the different vegetation covers present in Araucarias National Park; for that, it is intended to identify the medial values of EVI during the whole time series for different types of coverage of soil use and occupation, analyzing the relation between the phenological variations with precipitation data and maximum temperature, representing these variations of amplitude, phase and additive term for a complete series and individually for each year. Based on the HANTS algorithm, the harmonic analysis was applied to a time series of ten years, comprised between 2006 and 2015. Starting from this processing, images of the phase, amplitude and additive term were analyzed by means of four previously selected samples, representing the four main vegetation covers present in the park. In order to assist the visual interpretation of data, the images were converted from RGB to HLS. When all data was generated, it was possible to characterize how the variation in the value of vegetation indices happen throughout the year, as well as the time of the year when the biggest variations occur. Besides, it is possible to indicate the areas with significant changes in the use of soil, or changes caused by climatic events or by the vegetation own development. Through the data extracted with the harmonic analysis and the identification of the different phenologies, a classification was also generated on the time series, in order to identify the areas that still present remnants of Araucaria angustifolia predominantly.Ultimately, it is concluded that the application of a methodology based on the harmonic series enables a better comprehension of the forest covers present in this unity of conservation, generating useful information for the management and possible review of the management plan. For future application, the use of this methodology in a time series with greater spatial resolution is expected.