Performance and power consumption are most important issues while designing embedded systems. Several studies have shown that cache memory consumes about 50% of the total power in these systems. Thus, the architecture of the cache governs both performance and power usage of embedded systems. A new N-way reconfigurable data cache is proposed especially for embedded systems. This thesis explores the issues and design considerations involved in designing a reconfigurable cache. The proposed reconfigurable data cache architecture can be configured as direct-mapped, two-way, or four-way set associative using a mode selector. The module has been designed and simulated in Xilinx ISE 9.1i and ModelSim SE 6.3e using the Verilog hardware description language.

Off-highway vehicles are on the verge of switching from analog to digital video camera technology (VCT), which offers better video quality and new features but adds complexity to the system. This thesis project aims to implement the digital VCT to the display computer CCpilot VA intended for off-highway vehicles. In this project the differences between analog and digital VCTs were reviewed and then a demo displaying a live digital camera video feed on the embedded Linux based display computer CCpilot VA was implemented with Qt and QML. More specifically, different GStreamer pipelines were tested, as Qt uses GStreamer to play video, and camera settings were changed using the ISO 17215 standard.  The demo displayed a live digital camera video feed with high quality, low latency and high frame rate on the VA by using a GStreamer pipeline utilizing hardware decoding. The results have shown that digital video cameras perform better than analog cameras, primarily because digital cameras have better video quality. The attempts to simultaneously display a video feed and a Graphical User Interface created by Qt have been made. However, they were only successful with poor video performance. A zero-copy link between the GStreamer pipeline’s decoder and sink element must be used to obtain good video performance.

Thesis advisor: Robert J. Starratt / This case study examined teacher collaboration and teacher change while in the process of differentiating instruction in the area of mathematics in an elementary school. The project included a two-tier professional development opportunity for the staff. Professional development sessions focusing on specific mathematics skills were offered in lieu of traditional faculty meetings and thirteen, teacher volunteers in grades K-3 participated in bi-monthly study groups. The study describes the journey of the thirteen teachers as they identified successful strategies for differentiating instruction to meet the needs of all learners. The study explored how job-embedded professional development offered teachers the resources and support to meet together during the school day to engage in dialogue about their students' progress, difficulties encountered when teaching specific concepts and skills, and proactively planning in order to differentiate instruction effectively. The study focused on collaboration as a method for learning together in an adult learning environment and improving current teacher practices. The research was qualitative with the school principal as both researcher and participant-observer of the study. Data instruments used for the participants involved in this study were pre- and post-implementation surveys of the entire staff, semi-structured interviews of the thirteen teacher volunteers, observations of meetings, teachers' reflective journals, and field notes. Findings indicated that there was an increase in the teachers' use of differentiated instruction in the area of math. While teachers most often differentiated lessons by ability, teachers experimented with differentiating by interest as well as addressing the students' varying learning styles. In addition, teachers found that the embedded study groups were valuable in helping them to collaborate with their peers and improve their practice in teaching mathematics to all learners. In a profession where continual renewal is necessary, it is essential for educators to be provided with adequate time to review current practices, reflect on the strategies that are most successful, and refine their craft in order to provide opportunities that will maximize student thinking and learning. / Thesis (EdD) — Boston College, 2009. / Submitted to: Boston College. Lynch School of Education. / Discipline: Educational Administration and Higher Education.

Embedded contact homology is an invariant of closed oriented contact 3-manifolds first defined by Hutchings, and is isomorphic to both Heegard Floer homology (by the work of Colin, Ghiggini and Honda) and Seiberg-Witten Floer cohomology (by the work of Taubes). The embedded contact chain complex is defined by counting closed orbits of the Reeb vector field and certain pseudoholomorphic curves in the symplectization of the manifold. As part of their proof that ECH=HF, Colin, Ghiggini and Honda showed that if the contact form is suitably adapted to an open book decomposition of the manifold, then embedded contact homology can be computed by considering only orbits and differentials in the complement of the binding of the open book; this fact was then in turn used to define a knot version of embedded contact homology, denoted ECK, where the (null-homologous) knot in question is given by the binding. In this thesis we start by generalizing these results to the case of rational open book decompositions, allowing us to define ECK for rationally null-homologous knots. In its most general form this is a bi-filtered chain complex whose homology yields ECH of the closed manifold. There is also a hat version of ECK in this situation which is equipped with an Alexander grading equivalent to that in the Heegaard Floer setting, categorifies the Alexander polynomial, and is conjecturally isomorphic to the hat version of knot Floer homology. The main result of this thesis is a large negative $n$-surgery formula for ECK. Namely, we start with an (integral) open book decomposition of a manifold with binding $K$ and compute, for all $n$ greater than or equal to twice the genus of $K$, ECK of the knot $K(-n)$ obtained by performing ($-n$)-surgery on $K$. This formula agrees with Hedden's large $n$-surgery formula for HFK, providing supporting evidence towards the conjectured equivalence between the two theories. Along we the way, we also prove that ECK is, in many cases, independent of the choices made to define it, namely the almost complex structure on the symplectization and the homotopy type of the contact form. We also prove that, in the case of integral open book decompositions, the hat version of ECK is supported in Alexander gradings less than or equal to twice the genus of the knot.

Traditional SPICE simulation tools and applications of circuit theory lack real-time interaction and feedback. The goal of this thesis was to create an interactive physical environment to allow the manipulation and simulation of discrete electrical components in near-real-time while optimizing and streamlining the human-computer interaction (HCI) elements to make the user experience as positive and transparent as possible. This type of HCI and near-real-time simulation feedback would allow for the instant realization of how the parameters of each discrete component or hardware module affect the overall simulation and response of the circuit. The scope of this thesis is to research, design and develop two real-time interactive SPICE simulation tools and analyze the real-time benefits and HCI elements of both simulators, principally the user interface design itself. The first real-time interactive simulator (TouchSPICE) uses multiple embedded processors (touchscreen hardware blocks) and a host computer to build and simulate a circuit. The second real-time interactive simulator (ReActive-SPICE) uses a single host computer with integrated software to build and simulate a circuit, much like LTspice™ and PSpice™ without the real-time aspects. As part of the study, 20 students were asked to create circuits utilized in undergraduate-level labs using TouchSPICE and ReActive-SPICE for the sole purpose of providing feedback on the two user interfaces. Students were asked to complete a survey before, during and after circuit creation to provide a basis for judging the intuitiveness, efficiency and overall effectiveness of the HCIs. Conclusions based-off the surveys support the hypothesis that both TouchSPICE and ReActive-SPICE were more intuitive and overall simpler than traditional SPICE simulation tools. Feedback collected showed TouchSPICE to have a more intuitive user interface while ReActive-SPICE proved to be more efficient. ReActive-SPICE was further developed and enhanced to improve the user interface as well as the overall circuit creation and real-time simulation processes.

The demand for computing power and performance in real-time embedded systems is continuously increasing since new customer requirements and more advanced features are appearing every day. To support these functionalities and handle them in a more efficient way, multi-core computing platforms are introduced. These platforms allow for parallel execution of tasks on multiple cores, which in addition to its benefits to the system's performance introduces a major problem regarding the timing predictability of the system. That problem is reflected in unpredictable inter-core interferences, which occur due to shared resources among the cores, such as the system bus. This thesis investigates the application of different optimization techniques for the offline scheduling of tasks on the individual cores, together with a global scheduling policy for the access to the shared bus. The main effort of this thesis focuses on optimizing the inter-core data propagation delays which can provide a new way of creating optimized schedules. For that purpose, Constraint Programming optimization techniques are employed and a Phased Execution Model of the tasks is assumed. Also, in order to enforce end-to-end timing constraints that are imposed on the system, job-level dependencies are generated prior and subsequently applied during the scheduling procedure. Finally, an experiment with a large number of test cases is conducted to evaluate the performance of the implemented scheduling approach. The obtained results show that the method is applicable for a wide spectrum of abstract systems with variable requirements, but also open for further improvement in several aspects.

Aus der Vision, Computertechnik für den schmalen Geldbeutel technisch interessierten Jugendlichen verfügbar zu machen entstand ein kreditkartengroßer Einplatinencomputer, der Raspberry Pi. Wir möchten den Raspi im Vortrag etwas näher vorstellen und in einer kleinen Demonstration Anregungen für eigene Projekte geben. Gespannt sind wir auch auf Projekte, welche die Zuhörer bereits mit dem Raspberry Pi umgesetzt haben.

With continuous advancement in silicon technology and high feature demands on consumer electronics, the complexity of embedded software has led the software development effort to dominate System-On-Chip (SoC) design. Virtual Prototype (VP) addresses the problem by enabling early software development before hardware arrival. However, VP still poses challenges: 1) Instruction Set Simulator (ISS) degrades simulation time, 2) Development is restricted to embedded processor specific tools and 3) Applications and drivers are dependent on system software completion. In this work, we propose an abstraction framework which: 1) Removes ISS from VP, achieving native host software execution time, 2) Activates rich suites of desktop development tools in host by compiling embedded software in host binary and 3) Allows system software independent application and driver development. With this framework, we successfully demonstrated up to 2000% speed-up in VP run-time over conventional VP and improved software development productivity significantly.

With continuous advancement in silicon technology and high feature demands on consumer electronics, the complexity of embedded software has led the software development effort to dominate System-On-Chip (SoC) design. Virtual Prototype (VP) addresses the problem by enabling early software development before hardware arrival. However, VP still poses challenges: 1) Instruction Set Simulator (ISS) degrades simulation time, 2) Development is restricted to embedded processor specific tools and 3) Applications and drivers are dependent on system software completion. In this work, we propose an abstraction framework which: 1) Removes ISS from VP, achieving native host software execution time, 2) Activates rich suites of desktop development tools in host by compiling embedded software in host binary and 3) Allows system software independent application and driver development. With this framework, we successfully demonstrated up to 2000% speed-up in VP run-time over conventional VP and improved software development productivity significantly.

SIMD parallelism offers a high performance and efficient execution approach for today's broad range of portable multimedia consumer products. However, new methods are needed to meet the complex demands of high performance, embedded systems. This research explores new storage management techniques for this focused but critical application. These techniques include memory design exploration based on the application retargeting technique, storage-based systolic instruction broadcast, and systolic virtual memory to improve both the performance and efficiency of embedded SIMD systems. For an efficient storage usage by memory design space exploration in embedded SIMD systems, an analysis method for assessing storage needs and costs of a given application automatically retargeted across a spectrum of storage configuration designs was developed. Using this technique, a SIMD processing element achieves optimal area and energy efficiency with a register file containing between 8 and 12 words for given workload. This configuration is between 15% and 25% more area and energy efficient than other memory configurations being considered. Systolic instruction broadcast is a high performance and area efficient instruction broadcasting scheme with short-wire interconnects by eliminating of wire latency bottleneck found in global instruction broadcast. Three implementation methods are defined and evaluated - software method, 2-write port register file method, and bypass method. In our evaluations, due to the system's short clock cycle time and scheduler, a speedup in system performance of up to 7.5 can be achieved by the year 2010. In addition, speedup of area efficiency also can be achieved up to 7.2 for a given workload. The ability of minimizing off-chip memory access latency while maximizing access frequency by scheduling techniques along with data prefetch techniques in systolic virtual memory mechanism was evaluated using our SIMD-systolic architecture simulator. Results show that, systolic virtual off-chip memory with shared address space can achieve over 50% higher area efficiency than that of an on-chip only system for a matrix multiplication application.