Ένα rover όπως το Sojourner είναι, ή τουλάχιστον περιέχει μέσα του, ένα ενσωματωμένο σύτημα. Με τον όρο ενσωματωμένο σύστημα εννοούμε κάθε υπολογιστικό σύστημα το οποίο είναι σχεδιασμένο να εκτελεί συγκεκριμένες λειτουργίες για τον έλεγχο ενός μεγαλύτερου και ευρύτερου συστήματος. Πρόκειται λοιπόν για ένα σύστημα που εξυπηρετεί έναν εξειδικευμένο σκοπό σε αντίθεση π.χ. με τους προσωπικούς υπολογιστές, που είναι γενικού σκοπού. Ένα τέτοιο ενσωματωμένο σύστημα επιχειρήσαμε να κατασκευάσουμε στα πλαίσια αυτής της διπλωματικής εργασίας, για να μπορέσουμε να ελέγξουμε ένα δικό μας όχημα. Το όχημα μας και το γενικότερο θέμα της διπλωματικής έχει ως πρότυπο το Sojourner, το πρώτο όχημα που κινήθηκε στην επιφάνεια του Άρη, και στο βαθμό που είναι εφικτό θα το αναπαράγουμε. Σε αυτό το σημείο είναι καλό να επισημάνουμε ότι παρά την ιδιαίτερη πηγή έμπνευσης αυτής της εργασίας, οι εφαρμογές που έχει ένα rover δεν περιορίζονται στη πλανητική εξερεύνηση. Μπορούν να χρησιμοποιηθούν σε κάθε περίπτωση όπου η πρόσβαση για τον άνθρωπο είναι δύσκολη ή επικίνδυνη. Ένα κατάλληλα εξοπλισμένο rover για παράδειγμα μπορεί να αντικασταστήσει τα μάτια και τα χέρια του ανθρώπου στο εσωτρικό ενός πυρηνικού αντιδραστήρα ή ενός ηφαιστείου, όπου οι συνθήκες καθιστούν την ανθρώπινη παρουσία αδύνατη. Μια άλλη περίπτωση όπου ένα rover είναι χρήσιμο πάνως στη γη είναι σε αποστολές διάσωσης ανθρώπων σε συντρίμια κτηρίων όπου η απόκτηση εικόνας είναι δύσκολη. Εκτός αυτού οι δομές που θα υλοποιήσουμε και το hardware που θα χρησιμοποιήσουμε, είναι βασικές για κάθε ενσωματωμένο σύστημα. Οπότε πολλά επιμέρους κομμάτια της εργασίας έχουν αξία αφ’εαυτού τους. Για παράδειγμα η υλοποίηση ενός συστήματος ασύρματης επικοινωνίας έχει ευρύτατες εφαρμογές σήμερα. Το ίδιο ισχύει και για ένα λειτουργικό συστήμα που θα καλύπτει real time περιορισμούς, κάτι απαραίτητο για τη πλειοψηφία των ενσωματωμένων συστημάτων. Από αυτά γίνεται αντιληπτή η σημασία που έχει ο σχεδιασμός και η κατασκευή του οχήματος μας. Οι δυνατότητες που θέλουμε να έχει το δικό μας όχημα κινούνται στα 5 σημεία που αναφέραμε ότι είναι κοινά σε όλα τα rovers. Φυσικά κάποια στοιχεία όπως εξειδικευμένα επιστημονικά εργαλεία, τα οποία συλλέγουν δείγματα, δεν θα ενσωματωθούν. Δεν θα ενσωματωθούν ούτε μηχανισμοί προστασίας, προφανώς, από τις δύσκολες συνθήκες ( ακραίες θερμοκρασίες, ακτινοβολία ) που επικρατούν στο διάστημα και σε ξένους πλανήτες. Επίσης αν και θα προστεθεί ένας μηχανισμός ανίχνευσης εμποδίων, ώστε το σύστημα να γίνει αυτόνομο, δεν θα γίνει καμία αναφορά σε αυτό, στο παρών έγγραφο, καθώς αποτελεί αντικείμενο του δευτέρου μέρους αυτού του εγχειρήματος και κομμάτι άλλης διπλωματικής εργασίας. Ο στόχος λοιπόν αυτής της διπλωματικής είναι να κατασκευαστεί το όχημα με μία βασική λειτουργικότητα. Αυτό πρακτικά σημαίνει ότι θα χρειαστεί, πρώτον να δημιουργήσουμε ή να προμηθευτούμε τα μηχανικά μέρη που θα αποτελέσουν το σκελετό του οχήματος και να τον συνθέσουμε και δεύτερον να επιλεγεί το hardware που θα με το σωστό προγραμματισμό θα δίνει στο όχημα μας τις δυνατότητες που θέλουμε. Θα χρειαστεί δηλαδή να σχεδιάσουμε ένα βασικό λειτουργικό σύστημα που θα καλύπτει τις όποιες ανάγκες και περιορισμούς μας. Στο τέλος θα έχουμε ένα όχημα το οποίο θα μπορούμε να ελέγχουμε ασύρματα από έναν υπολογιστή. Το όχημα αυτό θα έχει τις βάσεις, είτε όσον αφορά το hardware, είτε όσον αφορά το software, ώστε να είναι δυνατή η προσθήκη επιπλέον υλικού, εξαρτημάτων και υπολογιστικών διεργασιών. / The aim of this diploma thesis is the creation of embedded system based on a 8086 microprocessor for the purpose of operating a vehicle and remotely controlling it through ZigBee PRO network.

With autonomous trucks on the road where the driver is absent requires new diagnostic methods. The driver possess several abilities which a machine does not. In this thesis, the use of machine learning as a method was investigated. A more concrete problem description was formed where the main objective was detecting anomalies in wheel configurations. More specifically, the machine learning model was used to detect incorrect wheel settings. Three different algorithms was used, SVM, LDA and logistic regression. Overall, the classifier predicts with high accuracy supporting that machine learning can be used for diagnosing autonomous vehicles.

This thesis designs, and partially implements, an architecture for running an embedded Linux application on a regular PC, without access to the target device. This thesis shows how a standard Linux User space filesystem, in the right environment, can be used to emulate the most common User space GPIO interface in Linux, SysFS. Furthermore, this thesis sets up a template for how this architecture can be used to run both the embedded application and an application emulating the connected hardware.

Today in farming of vegetables large amounts of water and pesticide are used, the farming is also weather and climate dependent and in Sweden the farming season is short. So, there is a need to make farming more efficient and determine how to make farming more stable and independent from unpredictable events. The goal of this project is to develop a prototype which make it possible to improve the resource usage and at the same time automate the process to increase the predictability. This project is going to use aeroponics which is way of growing in the air without soil and a single board computer is going to be used.

A constante redução nas dimensões dos transistores foi o principal combustível capaz de manter o crescente desempenho exigido por aplicações. Ao mesmo tempo, as tensões de alimentação dos circuitos também são reduzidas a cada novo nó tecnológico, fazendo com que partículas como nêutrons e partículas alpha, portando quantidades de energia cada vez menores sejam capazes de gerar os chamados soft errors, que impactam diretamente na redução da confiabilidade dos sistemas embarcados atuais. Isto faz com que a implementação de técnicas de tolerância a falhas se tornem praticamente obrigatórias para tecnologias atuais e futuras. Estes mesmos sistemas embarcados, como smartphones, devem apresentar alto poder de processamento, visando atender um crescente conjunto de aplicações de natureza heterogênea, consumindo a mínima potência possível. Nestes sistemas, algumas dessas principais aplicações como codec GSM, cancelamento de eco acústico, processamento de áudio e vídeo apresentam em comum a necessidade de multiplicar matrizes de diferentes dimensões em determinados intervalos de tempo. Pensando nestas demandas, será proposta a arquitetura RA3, cujo objetivo é executar o algoritmo de multiplicação de matrizes em paralelo com a técnica de tolerância a falhas conhecida na literatura como ABFT, visando a aumentar a confiabilidade da mesma. Além disso, a RA3 possui uma estrutura adaptativa que permite que unidades internas como memórias, multiplicadores e somadores sejam ligadas ou desligadas através da aplicação da técnica de power gating em tempo de execução, conforme restrições impostas pela largura da banda de memória, power budgets e deadlines impostos por aplicações de tempo real, visando executar tarefas consumindo a mínima potência possível. Para avaliar as funcionalidades propostas, dois estudos de caso reais são apresentados e o comportamento da arquitetura é avaliado sobre diversos aspectos como desempenho, área, consumo de potência e cobertura de falhas. Finalmente é possível comprovar que a adaptabilidade proposta pela arquitetura RA3 permite que seja encontrada, em diversos cenários, a quantidade exata de recursos necessários para executar determinadas aplicações sem comprometer as restrições impostas principalmente no consumo de potência e por aplicações com deadlines críticos, mantendo ainda altas taxas de cobertura de falhas. / The continuous reduction of transistors’ dimensions was the main drive capable of maintaining the performance increase required by applications. At the same time, supply voltages of the circuits are also reduced with each new technology node, causing particles such as neutrons or alpha particles, even with reduced amounts of energy, to generate so-called soft errors that directly impact on the reliability of embedded systems. This scenario makes the implementation of techniques for fault tolerance mandatory for current and future technologies. Still, embedded systems, such as smartphones, must provide high processing power to execute a growing set of applications of heterogeneous nature, consuming the least possible power. In these systems, applications like GSM codec, acoustic echo cancellation, audio and video processing have in common the need for matrix multiplication operations of different dimensions at certain time intervals. To efficiently support the aforementioned scenario, this dissertation proposes the RA3 architecture whose goal is run the matrix multiplication algorithm in parallel with the fault tolerance technique know in the literature as ABFT, aiming to support software execution with high reliability. Furthermore, the RA3 architecture provides adaptive internal units such as memories, multipliers and adders with adaptive powering on or off by applying power gating at runtime. Runtime power gating enables to meet restrictions imposed by real-time applications or memory bandwidth with minimum power. To evaluate the proposed architecture, two case studies are presented and the behavior of the architecture is evaluated in terms of performance, area, power consumption and fault coverage. Finally, a comprehensive design space exploration shows that the adaptability provided by the RA3 architecture allows the system designer to find, in many scenarios, the exact amount of resources needed to run a set of applications without compromising the restrictions imposed mainly in power consumption and real-time deadlines, while still maintaining a high fault coverage rate.

Técnicas que partem de modelos de alto nível de abstração são requeridas para lidar com a complexidade encontrada nas novas gerações de sistemas embarcados, sendo cruciais para o sucesso do projeto. Uma grande redução do esforço pode ser obtida com o uso de modelos quando código em uma linguagem de programação pode ser gerado automaticamente a partir desses. Porém, ferramentas disponíveis para modelagem e geração de código normalmente são dependentes de domínio e o software embarcado normalmente possui comportamento heterogêneo, requerendo suporte a múltiplos modelos de computação. Nesta tese, estratégias para desenvolvimento de software embarcado baseado em modelos de alto nível usando UML e Simulink são analisadas. A partir desta análise, observaram-se as principais limitações das abordagens para geração de código baseadas em UML e Simulink. Esta tese, então, propõe estratégias para melhorar a automação provida por estas ferramentas, como por exemplo, propondo uma abordagem para geração de código multithread a partir de modelos Simulink. A comparação feita entre UML e Simulink mostra que, embora UML seja a linguagem mais usada no domínio de engenharia de software, UML é baseada em eventos e não é adequada para modelar sistemas dataflow. Por outro lado, Simulink é largamente usado por engenheiros de hardware e de controle, além de suportar dataflow e geração de código. Porém, Simulink provê abstrações de mais baixo nível, quando comparado a UML. Conclui-se que tanto UML como Simulink possuem prós e contras, o que motiva a integração de ambas linguagens em um único fluxo de projeto. Neste contexto, esta tese propõe também uma abordagem integradora para desenvolvimento de software embarcado que inicia com uma especificação de alto nível descrita usando diagramas UML, a partir da qual modelos dataflow e control-flow podem ser gerados. Desta maneira, o modelo UML pode ser usado como front-end para diferentes abordagens de geração de código, incluindo UML e a proposta geração de código multithread a partir de modelos Simulink. / The use of techniques starting from higher abstraction levels is required to cope with the complexity that is found in the new generations of embedded systems, being crucial to the design success. A large reduction of design effort when using models in the development can be achieved when there is a possibility to automatically generate code from them. Using these techniques, the designer specifies the system model using some abstraction and code in a programming language is generated from that. However, available tools for modeling and code generation are domain-specific and embedded software usually shows heterogeneous behavior, which pushes the need for supporting software automation under different models of computation. In this thesis, strategies for embedded software development based on high-level models using UML and Simulink were analyzed. We observed that the embedded software generation approaches based on UML and Simulink have limitations, and hence this thesis proposes strategies to improve the automation provided on those approaches, for example, proposing a Simulink-based multithread code generation. UML is a well used language in the software engineering domain, and we consider that it has several advantages. However, UML is event-based and not suitable to model dataflow systems. On the other side, Simulink is widely used by control and hardware engineers and supports dataflow, and time-continuous models. Moreover, tools are available to generate code from a Simulink model. However, Simulink models represent lower abstraction level compared to UML ones. This comparison shows that UML and Simulink have pros and cons, which motivates the integration of both languages in a single design process. As the main contribution, we propose in this thesis an integrated approach to embedded software design, which starts from a high-level specification using UML diagrams. Both dataflow and control-flow models can be generated from that. In this way, an UML model can be used as front-end for different code generation approaches, including UML-based one and the proposed Simulink-based multithread code generation.

Memórias cache são tradicionalmente desabilitadas em aplicações espaciais e críticas porque acredita-se que a área sensível por elas introduzida comprometeria a confiabilidade do sistema. Conforme a tecnologia tem evoluído, a diferença de velocidade entre lógica e memória principal tem aumentado de tal maneira que desabilitando as caches a execução do código é retardada muito mais do que no passado. Como resultado, o processador fica exposto por um tempo muito maior para computar a mesma cargade trabalho. Neste trabalho nós demonstraremos que, em processadores embarcados modernos, habilitar as caches pode trazer benefícios para sistemas críticos: a área exposta maior pode ser compensada pelo tempo de exposição mais curto, levando a uma melhora total na confiabilidade. Nós propomos uma métrica intuitiva e um modelo matemático para avaliar a confiabilidade de um sistema em termos espaciais (i.e., área sensível à radiação) e temporais (i.e., desempenho), e provamos que minimizar a área sensível à radiação não necessariamente maximiza a confiabilidade da aplicação. A métrica e o modelo propostos são experimentalmente validados através de uma campanha extensiva de testes de radiação utilizando um Sistema-em-Chip de prateleira fabricado em 28nm baseado em processadores ARM como estudo de caso. Os resultados experimentais demonstram que, durante a execução da aplicação estudada à altitude de aeronave militar, a probabilidade de executar a carga de trabalho de uma missão de dois anos sem falhas é aumentada em 5.85% se as caches L1 são habilitadas (deste modo, aumentado a área sensível à radiação), quando comparada com nenhum nível de cache habilitado. Entretanto, se ambos níveis L1 e L2 são habilitados a probabilidade é diminuída em 31.59%. / Cache memories are traditionally disabled in space-level and safety-critical applications since it is believed that the sensitive area they introduce would compromise the system reliability. As the technology has evolved, the speed gap between logic and main memory has increased in such a way that disabling caches slows the code much more than in the past. As a result, the processor is exposed for a much longer time in order to compute the same workload. In this work we demonstrate that, on modern embedded processors, enabling caches may bring benefits to critical systems: the larger exposed area may be compensated by the shorter exposure time, leading to an overall improved reliability. We propose an intuitive metric and a mathematical model to evaluate system reliability in spatial (i.e., radiation-sensitive area) and temporal (i.e., performance) terms, and prove that minimizing radiation-sensitive area does not necessarily maximize application reliability. The proposed metric and model are experimentally validated through an extensive radiation test campaign using a 28nm off-the-shelf ARM-based Systemon- Chip as a case study. The experimental results demonstrate that, while executing the considered application at military aircraft altitude, the probability of executing a two-year mission workload without failures is increased by 5.85% if L1 caches are enabled (thus, increasing the radiation-sensitive area), when compared to no cache level being enabled. However, if both L1 and L2 caches are enabled the probability is decreased by 31.59%.

Atualmente, a adição de uma nova função implementada em hardware em um processador não deve impor nenhuma mudança no conjunto de instruções (ISA – Instruction Set Architecture) suportado para atingir melhorias em seu desempenho. O objetivo é manter a compatibilidade retroativa e futura de programas já compilados. Todavia, este fato se torna, muitas vezes, um fator impeditivo para o aprimoramento ou desenvolvimento de uma nova arquitetura. Desta maneira, a utilização de mecanismos de Tradução Binária abre novas oportunidades aos projetistas, já que estes mecanismos permitem a execução de programas já compilados em arquiteturas que suportam conjuntos de instruções diferentes do previsto inicialmente. Assim, para eliminar o custo adicional apresentado por estes sistemas de tradução, será proposto um novo mecanismo de tradução binária dinâmico de dois níveis. Enquanto o primeiro nível é responsável pela tradução de facto das instruções do conjunto nativo para instruções de uma linguagem de máquina intermediária, o segundo nível otimiza estas instruções já traduzidas para serem executadas na arquitetura alvo. O sistema é totalmente flexível, pois pode suportar a tradução de conjuntos de instruções completamente diferentes; assim como a utilização de arquiteturas de hardware com as mais diversas características. Este trabalho apresenta o primeiro esforço nesta direção: um estudo de caso onde ocorre a tradução de código x86 para MIPS (linguagem intermediária), que será otimizado para ser executado em uma arquitetura que realiza reconfiguração dinâmica. Resta demonstrado que é possível manter a compatibilidade binária, com melhoria no desempenho em torno de 45% em média e consumo de energia semelhante ao da execução nativa. / In these days, every new added hardware feature must not change the underlying instruction set architecture (ISA), in order to avoid adaptation or recompilation of existing code. Therefore, Binary Translation (BT) opens new possibilities for designers, previously tied to a specific ISA and all its legacy hardware issues, since it allows the execution of already compiled applications on different architectures. To overcome the BT inherent performance penalty, we propose a new mechanism based on a dynamic two-level binary translation system. While the first level is responsible for the BT de facto to an intermediate machine language, the second level optimizes the already translated instructions to be executed on the target architecture. The system is totally flexible, supporting the porting of radically different ISAs and the employment of different target architectures. This work presents the first effort towards this direction: it translates code implemented in the x86 ISA to MIPS assembly (the intermediate language), which will be optimized by the target architecture: a dynamically reconfigurable architecture. In this work is showed that is possible to maintain binary compatibility with performance improvements on average 45% and similar energy consumption when compared to native execution.

AN ABSTRACT OF THE THESIS OF KAUSHIK POLURI, for the Master of Science degree in Electrical and Computer Engineering, presented on 07/03/2013, at Southern Illinois University Carbondale. TITLE: Bounding the Worst-Case Response Times of Hard-Real-Time Tasks under the Priority Ceiling Protocol in Cache-Based Architectures MAJOR PROFESSOR: Dr. HARINI RAMAPRASAD Schedulability analysis of hard-real-time systems requires a-priori knowledge of the worst-case execution times (WCET) of all tasks. Static timing analysis is a safe technique used for calculating WCET that attempts to model program complexity, architectural complexity and complexity introduced by interference from other tasks. Modern architectural features such as caches make static timing analysis of a single task challenging due to unpredictability introduced by their reliance on the history of memory accesses and the analysis of a set of tasks even more challenging due to cache-related interference among tasks. Researchers have proposed several static timing analysis techniques that explicitly consider cache-eviction delays for independent hard-real-time tasks executing on cache-based architectures. However, there is little research in this area for resource-sharing tasks. Recently, an analysis technique was proposed for systems using the Priority Inheritance Protocol (PIP) to manage resource-arbitration among tasks. The Priority Ceiling Protocol (PCP) is a resource-arbitration protocol that offers distinct advantages over the PIP, including deadlock avoidance. However, to the best of our knowledge, there is currently no technique to bound the WCET of resource-sharing tasks under PCP with explicit consideration of cache-eviction delays. This thesis presents a technique to bound the WCETs and hence, the Worst-Case Response Times (WCRTs) of resource-sharing hard-real-time tasks executing on cache-based uniprocessor systems, specifically focusing on data cache analysis.

Técnicas que partem de modelos de alto nível de abstração são requeridas para lidar com a complexidade encontrada nas novas gerações de sistemas embarcados, sendo cruciais para o sucesso do projeto. Uma grande redução do esforço pode ser obtida com o uso de modelos quando código em uma linguagem de programação pode ser gerado automaticamente a partir desses. Porém, ferramentas disponíveis para modelagem e geração de código normalmente são dependentes de domínio e o software embarcado normalmente possui comportamento heterogêneo, requerendo suporte a múltiplos modelos de computação. Nesta tese, estratégias para desenvolvimento de software embarcado baseado em modelos de alto nível usando UML e Simulink são analisadas. A partir desta análise, observaram-se as principais limitações das abordagens para geração de código baseadas em UML e Simulink. Esta tese, então, propõe estratégias para melhorar a automação provida por estas ferramentas, como por exemplo, propondo uma abordagem para geração de código multithread a partir de modelos Simulink. A comparação feita entre UML e Simulink mostra que, embora UML seja a linguagem mais usada no domínio de engenharia de software, UML é baseada em eventos e não é adequada para modelar sistemas dataflow. Por outro lado, Simulink é largamente usado por engenheiros de hardware e de controle, além de suportar dataflow e geração de código. Porém, Simulink provê abstrações de mais baixo nível, quando comparado a UML. Conclui-se que tanto UML como Simulink possuem prós e contras, o que motiva a integração de ambas linguagens em um único fluxo de projeto. Neste contexto, esta tese propõe também uma abordagem integradora para desenvolvimento de software embarcado que inicia com uma especificação de alto nível descrita usando diagramas UML, a partir da qual modelos dataflow e control-flow podem ser gerados. Desta maneira, o modelo UML pode ser usado como front-end para diferentes abordagens de geração de código, incluindo UML e a proposta geração de código multithread a partir de modelos Simulink. / The use of techniques starting from higher abstraction levels is required to cope with the complexity that is found in the new generations of embedded systems, being crucial to the design success. A large reduction of design effort when using models in the development can be achieved when there is a possibility to automatically generate code from them. Using these techniques, the designer specifies the system model using some abstraction and code in a programming language is generated from that. However, available tools for modeling and code generation are domain-specific and embedded software usually shows heterogeneous behavior, which pushes the need for supporting software automation under different models of computation. In this thesis, strategies for embedded software development based on high-level models using UML and Simulink were analyzed. We observed that the embedded software generation approaches based on UML and Simulink have limitations, and hence this thesis proposes strategies to improve the automation provided on those approaches, for example, proposing a Simulink-based multithread code generation. UML is a well used language in the software engineering domain, and we consider that it has several advantages. However, UML is event-based and not suitable to model dataflow systems. On the other side, Simulink is widely used by control and hardware engineers and supports dataflow, and time-continuous models. Moreover, tools are available to generate code from a Simulink model. However, Simulink models represent lower abstraction level compared to UML ones. This comparison shows that UML and Simulink have pros and cons, which motivates the integration of both languages in a single design process. As the main contribution, we propose in this thesis an integrated approach to embedded software design, which starts from a high-level specification using UML diagrams. Both dataflow and control-flow models can be generated from that. In this way, an UML model can be used as front-end for different code generation approaches, including UML-based one and the proposed Simulink-based multithread code generation.