Dealing properly with electronics and software will be a strong competitive advantage in the automotive sector in the near future. Electronics are driving current innovations and are at the same time becoming a larger part of the cost of the vehicle. In order to be successful as an automotive manufacturer, innovations must be introduced in the vehicle without compromising the final price tag. Also, the electronics has to compete with, and win over, the dependability of well known and proven mechanical solutions. Structure related costs can be reduced by designing a modular system, volume related costs can be reduced by utilizing fewer electronic control units that shares software performing a variety of functions. To achieve a modular system careful consideration must be applied in the architecture design process. Architecting is commonly referred to as an art, performed in a qualitative manner. This thesis provides a quantitative method for architecture design and evaluation targeting modular architectures. The architecture design method is based on a simple underlying information model. This model is extended through practical experiences in case studies to include support for configuration and documentation. An information model is a key enabler for managing the increasing complexity of automotive embedded systems. The model provides the basis for establishing the analyzable documentation that is required to ensure the dependability of the systems, specifically in terms of need for reliability, maintainability and safety. An information model supports traceability both within the product, across components, and also between different organizational units using different views of the product throughout the lifecycle. Further, some general issues of systems engineering and model based development related to the engineering of automotive embedded systems are discussed. Considerations for introducing a model based development process are covered. Also, the maturity of development processes and requirements on tools in an automotive context are evaluated. The ideas and methods presented in this thesis have been developed and tried in an industrial setting through a range of case studies. / QC 20101027

The Internet has profoundly changed todays human being life. A variety of information and online services are offered by various companies and organizations via the Internet. Although these services have substantially improved the quality of life, at the same time they have brought new challenges and difficulties. The information security can be easily tampered by many threats from attackers for different purposes. A catastrophe event can happen when a computer or a computer network is exposed to the Internet without any security protection and an attacker can compromise the computer or the network resources for destructive intention.<p> The security issues can be mitigated by setting up a firewall between the inside network and the outside world. A firewall is a software or hardware network device used to enforce the security policy to the inbound and outbound network traffic, either installed on a single host or a network gateway. A packet filtering firewall controls the header field in each network data packet based on its configuration and permits or denies the data passing thorough the network.<p> The objective of this thesis is to design a highly customizable hardware packet filtering firewall to be embedded on a network gateway. This firewall has the ability to process the data packets based on: source and destination TCP/UDP port number, source and destination IP address range, source MAC address and combination of source IP address and destination port number. It is capable of accepting configuration changes in real time. An Altera FPGA platform has been used for implementing and evaluating the network firewall.

The increasing demand for new functionalities in current and future hard real-time embedded systems, like the ones deployed in automotive and avionics industries, is driving an increment in the performance required in current embedded processors. Multi-core processors represent a good design solution to cope with such higher performance requirements due to their better performance-per-watt ratio while maintaining the core design simple. Moreover, multi-cores also allow executing mixed-criticality level workloads composed of tasks with and without hard real-time requirements, maximizing the utilization of the hardware resources while guaranteeing low cost and low power consumption. Despite those benefits, current multi-core processors are less analyzable than single-core ones due to the interferences between different tasks when accessing hardware shared resources. As a result, estimating a meaningful Worst-Case Execution Time (WCET) estimation - i.e. to compute an upper bound of the application's execution time - becomes extremely difficult, if not even impossible, because the execution time of a task may change depending on the other threads running at the same time. This makes the WCET of a task dependent on the set of inter-task interferences introduced by the co-running tasks. Providing a WCET estimation independent from the other tasks (time composability property) is a key requirement in hard real-time systems. This thesis proposes a new multi-core processor design in which time composability is achieved, hence enabling the use of multi-cores in hard real-time systems. With our proposals the WCET estimation of a HRT is independent from the other co-running tasks. To that end, we design a multi-core processor in which the maximum delay a request from a Hard Real-time Task (HRT), accessing a hardware shared resource can suffer due to other tasks is bounded: our processor guarantees that a request to a shared resource cannot be delayed longer than a given Upper Bound Delay (UBD). In addition, the UBD allows identifying the impact that different processor configurations may have on the WCET by determining the sensitivity of a HRT to different resource allocations. This thesis proposes an off-line task allocation algorithm (called IA3: Interference-Aware Allocation Algorithm), that allocates tasks in a task set based on the HRT's sensitivity to different resource allocations. As a result the hardware shared resources used by HRTs are minimized, by allowing Non Hard Real-time Tasks (NHRTs) to use the rest of resources. Overall, our proposals provide analyzability for the HRTs allowing NHRTs to be executed into the same chip without any effect on the HRTs. The previous first two proposals of this thesis focused on supporting the execution of multi-programmed workloads with mixed-criticality levels (composed of HRTs and NHRTs). Higher performance could be achieved by implementing multi-threaded applications. As a first step towards supporting hard real-time parallel applications, this thesis proposes a new hardware/software approach to guarantee a predictable execution of software pipelined parallel programs. This thesis also investigates a solution to verify the timing correctness of HRTs without requiring any modification in the core design: we design a hardware unit which is interfaced with the processor and integrated into a functional-safety aware methodology. This unit monitors the execution time of a block of instructions and it detects if it exceeds the WCET. Concretely, we show how to handle timing faults on a real industrial automotive platform. / La creciente demanda de nuevas funcionalidades en los sistemas empotrados de tiempo real actuales y futuros en industrias como la automovilística y la de aviación, está impulsando un incremento en el rendimiento necesario en los actuales procesadores empotrados. Los procesadores multi-núcleo son una solución eficiente para obtener un mayor rendimiento ya que aumentan el rendimiento por vatio, manteniendo el diseño del núcleo simple. Por otra parte, los procesadores multi-núcleo también permiten ejecutar cargas de trabajo con niveles de tiempo real mixtas (formadas por tareas de tiempo real duro y laxo así como tareas sin requerimientos de tiempo real), maximizando así la utilización de los recursos de procesador y garantizando el bajo consumo de energía. Sin embargo, a pesar los beneficios mencionados anteriormente, los actuales procesadores multi-núcleo son menos analizables que los de un solo núcleo debido a las interferencias surgidas cuando múltiples tareas acceden simultáneamente a los recursos compartidos del procesador. Como resultado, la estimación del peor tiempo de ejecución (conocido como WCET) - es decir, una cota superior del tiempo de ejecución de la aplicación - se convierte en extremadamente difícil, si no imposible, porque el tiempo de ejecución de una tarea puede cambiar dependiendo de las otras tareas que se estén ejecutando concurrentemente. Determinar una estimación del WCET independiente de las otras tareas es un requisito clave en los sistemas empotrados de tiempo real duro. Esta tesis propone un nuevo diseño de procesador multi-núcleo en el que el tiempo de ejecución de las tareas se puede componer, lo que permitirá el uso de procesadores multi-núcleo en los sistemas de tiempo real duro. Para ello, diseñamos un procesador multi-núcleo en el que la máxima demora que puede sufrir una petición de una tarea de tiempo real duro (HRT) para acceder a un recurso hardware compartido debido a otras tareas está acotado, tiene un límite superior (UBD). Además, UBD permite identificar el impacto que las diferentes posibles configuraciones del procesador pueden tener en el WCET, mediante la determinación de la sensibilidad en la variación del tiempo de ejecución de diferentes reservas de recursos del procesador. Esta tesis propone un algoritmo estático de reserva de recursos (llamado IA3), que asigna tareas a núcleos en función de dicha sensibilidad. Como resultado los recursos compartidos del procesador usados por tareas HRT se reducen al mínimo, permitiendo que las tareas sin requerimiento de tiempo real (NHRTs) puedas beneficiarse del resto de recursos. Por lo tanto, las propuestas presentadas en esta tesis permiten el análisis del WCET para tareas HRT, permitiendo así mismo la ejecución de tareas NHRTs en el mismo procesador multi-núcleo, sin que estas tengan ningún efecto sobre las tareas HRT. Las propuestas presentadas anteriormente se centran en el soporte a la ejecución de múltiples cargas de trabajo con diferentes niveles de tiempo real (HRT y NHRTs). Sin embargo, un mayor rendimiento puede lograrse mediante la transformación una tarea en múltiples sub-tareas paralelas. Esta tesis propone una nueva técnica, con soporte del procesador y del sistema operativo, que garantiza una ejecución analizable del modelo de ejecución paralela software pipelining. Esta tesis también investiga una solución para verificar la corrección del WCET de HRT sin necesidad de ninguna modificación en el diseño de la base: un nuevo componente externo al procesador se conecta a este sin necesidad de modificarlo. Esta nueva unidad monitorea el tiempo de ejecución de un bloque de instrucciones y detecta si se excede el WCET. Esta unidad permite detectar fallos de sincronización en sistemas de computación utilizados en automóviles.

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Many efforts have been carried out to provide transmission reliability in the history of communication systems. As the demand for real-time applications increased, providing a reliable communication in a timely manner for such applications is strongly desired. Considering timing constraints makes the issue of achieving reliability more difficult. This thesis concentrates on providing reliability for real-time communication in embedded networks by achieving a timing analysis and using the ARQ concept. What is carried out in this thesis is providing retransmission in a real-time manner for embedded networks according to application request. The thesis work focuses on one packet retransmission over a point to point link, but the concept is rich and can be extended to cover application request in real-time embedded networks. Two methods have been fulfilled, and a simulation has been done on the timing analysis focusing on the performance in accepting real-time traffic in the form of separate channels for each application request. The protocol combines ARQ and a scheduling algorithm as a base to support retransmission for hard real-time applications in embedded networks.

This thesis describes the design and implementation of a Linux-based, Web-oriented operating system called Awesom-O, designed with a focus on short boot time and small disk footprint. Among other techniques for lowering boot time, a semi-automatic method for generating a Linux kernel of minimal size for a given platform is developed, making use of an interpreter for the Linux kernel’s configuration language, Kconfig. The boot process of the finished system is analyzed to identify limiting factors in lowering its boot time further, and techniques for overcoming these are suggested. Excluding the initial BIOS stage of the boot process, the boot time of the finished system—up until it is idling inside the web browser interface waiting for user input—is 3.8 seconds (2.1 seconds to a shell prompt, 1.7 seconds in the kernel) on an Acer Travelmate 8200 laptop with an Intel Core Duo CPU at 2.0 GHz and a Momentus 5400.2 SATA (ST9120821AS) hard drive; 2.4 seconds (1.6 seconds to a shell prompt, 1.1 seconds in the kernel) on a Celsius M460 workstation with an Intel Core 2 Quad CPU at 2.5 GHz and a Barracuda 7200.11 SATA hard drive (ST3500320AS); 4.6 and 4.0 seconds respectively for the same systems when booting from a USB 2.0 device (a ChipsBank CBM2080 USB 2.0 stick); and 12.6 seconds on the BeagleBoard (8 seconds in the bootloader—an obvious area for future improvement). The Web functionality in Awesom-O is implemented atop the Opera Linux Devices SDK: a software framework for integrating web browser functionality in small Linux-based systems.

In communication systems, the need for high bandwidth interconnects and efficient distribution of large amount of data is very essential. This thesis work addresses all-optical packet switching issues in the field of reconfigurable optical interconnection networks for high performance embedded systems. The recent research conducted at the Halmstad University, on high performance embedded systems, focuses on the optical interconnection techniques to achieve ultra high throughputs and reconfigurability at the system level. Recent research in the field of optical interconnection networks for applications like switches and routers for data and telecommunication industry and parallel computing architectures for embedded signal processing use optical to electrical conversion to switch packets. This conversion scales down the enormous bandwidth capacity of the optical communication channels to electronic processing rates. To maintain the high throughputs all over the interconnection networks, the optical packets need to be maintained in optical state and switched to different part of the interconnection network. To achieve this goal, all-optical packet switching architectures are studied. The study is concluded with a positive outlook towards alloptical switching technologies, and it will play a very important role in the near future in the field of optical communication, telecommunication and embedded systems.

The Internet has profoundly changed todays human being life. A variety of information and online services are offered by various companies and organizations via the Internet. Although these services have substantially improved the quality of life, at the same time they have brought new challenges and difficulties. The information security can be easily tampered by many threats from attackers for different purposes. A catastrophe event can happen when a computer or a computer network is exposed to the Internet without any security protection and an attacker can compromise the computer or the network resources for destructive intention.<p> The security issues can be mitigated by setting up a firewall between the inside network and the outside world. A firewall is a software or hardware network device used to enforce the security policy to the inbound and outbound network traffic, either installed on a single host or a network gateway. A packet filtering firewall controls the header field in each network data packet based on its configuration and permits or denies the data passing thorough the network.<p> The objective of this thesis is to design a highly customizable hardware packet filtering firewall to be embedded on a network gateway. This firewall has the ability to process the data packets based on: source and destination TCP/UDP port number, source and destination IP address range, source MAC address and combination of source IP address and destination port number. It is capable of accepting configuration changes in real time. An Altera FPGA platform has been used for implementing and evaluating the network firewall.

Multiple trends in computer architecture are beginning to collide as process technology reaches ever smaller feature sizes. Problems with managing power, access times across a die, and increasing complexity to sustain growth are now blocking commercial products like the Pentium 4. These problems also occur in the embedded system space, albeit in a slightly different form. However, as process technology marches on, today's high-performance space is becoming tomorrow's embedded space. New techniques are needed to overcome these problems. In this thesis, we propose a novel architecture called SoftCache to address these emerging issues for embedded systems. We reduce the on-die memory controller infrastructure which reduces both power and space requirements, using the ubiquitous network device arena as a proving ground of viability. In addition, the SoftCache achieves further power and area savings by converting on-die cache structures into directly addressable SRAM and reducing or eliminating the external DRAM. To avoid the burden of programming complexity this approach presents to the application developer, we provide a transparent client-server dynamic binary translation system that runs arbitrary ELF executables on a stripped-down embedded target. One drawback to such a scheme lies in the overhead of additional instructions required to effect cache behavior, particularly with respect to data caching. Another drawback is the power use when fetching from remote memory over the network. The SoftCache comprises a dynamic client-server translation system on simplified hardware, targeted at Intel XScale client devices controlled from servers over the network. Reliance upon a network server as a ``backing store' introduces new levels of complexity, yet also allows for more efficient use of local space. The explicitly software managed aspects create a cache of variable line size, full associativity, and high flexibility. This thesis explores these particular issues, while approaching everything from the perspective of feasibility and actual architectural changes.