With increasing complexity and software content, modern embedded platforms employ a heterogeneous mix of multi-core processors along with hardware accelerators in order to provide high performance in limited power budgets. Due to complex interactions and highly dynamic behavior, static analysis of real-time performance and other constraints is challenging. As an alternative, full-system simulations have been widely accepted by designers. With traditional approaches being either slow or inaccurate, so-called host-compiled simulators have recently emerged as a solution for rapid evaluation of complete systems at early design stages. In such approaches, a faster simulation is achieved by natively executing application code at the source level, abstracting execution behavior of target platforms, and thus increasing simulation granularity. However, most existing host-compiled simulators often focus on application behavior only while neglecting effects of hardware/software interactions and associated speed and accuracy tradeoffs in platform modeling. In this dissertation, we focus on host-compiled operating system (OS) and processor modeling techniques, and we introduce novel dynamic timing model management approaches that efficiently improve both accuracy and speed of such models via automatically calibrating the simulation granularity. The contributions of this dissertation are twofold: We first establish an infrastructure for efficient host-compiled multi-core platform simulation by developing (a) abstract models of both real-time OSs and processors that replicate timing-accurate hardware/software interactions and enable full-system co-simulation, and (b) quantitative and analytical studies of host-compiled simulation principles to analyze error bounds and investigate possible improvements. Building on this infrastructure, we further propose specific techniques for improving accuracy and speed tradeoffs in host-compiled simulation by developing (c) an automatic timing granularity adjustment technique based on dynamically observing system state to control the simulation, (d) an out-of-order cache hierarchy modeling approach to efficiently reorder memory access behavior in the presence of temporal decoupling, and (e) a synchronized timing model to align platform threads to run efficiently in parallel simulation. Results as applied to industrial-strength platforms confirm that by providing careful abstractions and dynamic timing management, our models can achieve full-system simulations at equivalent speeds of more than a thousand MIPS with less than 3% timing error. Coupled with the capability to easily adjust simulation parameters and configurations, this demonstrates the benefits of our platform models for early application development and exploration. / text

This dissertation shows that with simple programming abstractions, network-wide resource coordination is efficient and useful for programming embedded sensor networks. Existing systems have focused primarily on managing resources for individual nodes, but a sensor network is not merely a collection of nodes operating independently: it must coordinate behavior across multiple nodes to achieve high efficiency. We need tools that can enable system-wide coordination at a higher level of abstraction than what exists today. We present three core contributions. The first is a service called IDEA that enables networkwide energy management for sensor networks. It unites energy monitoring, load modeling, and distributed state sharing into a single service that facilitates distributed decision making. Using simulation and testbed results, we show that IDEA enables improvements in network lifetime of up to 35% over approaches that do not consider energy distribution. Our second contribution is Karma, a system for coordinating insect-sized robotic microaerial vehicle (MAV) swarms, an emerging class of mobile sensor networks. Karmas system architecture simplifies the functionality of an individual MAV to a sequence of sensing and actuation commands called behaviors. Each behavior has an associated progress function, a measure of how much of that behavior has been completed. Programming is done by composing behaviors which are coordinated using input from the progress functions. Through simulation and testbed experiments, we demonstrate Karma applications can run on limited resources, are robust to individual MAV failure, and adapt to changes in the environment. Our final contribution is Simbeeotic, a testbed for MAV coordination algorithms. MAV sensors must be codesigned with the software and coordination algorithms that depend on them. This requires a testbed capable of simulating sensors to evaluate them before actual hardware is available and the ability to test with real flight dynamics for accurate control evaluation. In addition, simulation should be able to scale to hundreds or thousands of MAVs at a reduced level of fidelity in order to test at scale. We demonstrate that Simbeeotic provides the appropriate level of fidelity to evaluate prototype systems while maintaining the ability to test at scale. / Engineering and Applied Sciences

Το πρότυπο IEC61499 ορίζει το Function Block ως νέο τρόπο ανάπτυξης συστημάτων ελέγχου και αυτοματισμού. Τα συστήματα αυτά αποτελούνται από κατανεμημένες, ενσωματωμένες συσκευές οι οποίες διασυνδέονται μέσω βιομηχανικών δικτύων πραγματικού χρόνου. Λόγω του κατανεμημένου χαρακτήρα των συστημάτων αυτών, η εύρεση και επιδιόρθωση σφαλμάτων και ο έλεγχος της ορθής λειτουργίας τους θα πρέπει να γίνεται στο περιβάλλον των ενσωματωμένων αυτών συστημάτων. Στα πλαίσια αυτής της διπλωματικής δίνεται μία υλοποίηση για την κάλυψη της παραπάνω ανάγκης. Ο χρήστης μέσω μίας γραφικής διεπαφής, έχει την δυνατότητα να εκτελεί βασικές λειτουργίες απασφαλμάτωσης στο περιβάλλον των ενσωματωμένων συστημάτων, σε πραγματικό χρόνο, με την χρήση του RTAI και του RTnet. / The IEC 61499 standard defines Function Block as a new way of developing control and automation systems. These systems consist of distributed embedded devices which interconnect via real time industrial networks. Due to the distributive character of these systems, debugging and operation integrity check, should be done on target environment. This dissertation provides a tool for covering this need. Via a graphical user interface the user has the ability to perform basic real time debugging operations in the target enviroment, using RTAI and RTnet.

Navigation algorithms integrating measurements from multi-sensor systems overcome the problems that arise from using GPS navigation systems in standalone mode. Algorithms which integrate the data from 2D low-cost reduced inertial sensor system, consisting of a gyroscope and an odometer, along with a GPS via a Kalman filter has proved to be worthy in providing a consistent and more reliable navigation solution compared to the standalone GPS. It has been also shown to be beneficial, especially in GPS-denied environments such as urban canyons and tunnels. The main objective of this research is to narrow the idea-to-implementation gap that follows the algorithm development by realizing a low-cost real-time embedded navigation system that is capable of computing the data-fused positioning solution instantly. The role of the developed system is to synchronize the measurements from the three sensors, GPS, gyroscope and odometer, relative to the pulse per second signal generated from the GPS, after which the navigation algorithm is applied to the synchronized measurements to compute the navigation solution in real-time. Xilinx’s MicroBlaze soft-core processor on a Virtex-4 FPGA is utilized and customized for developing the real-time navigation system. The soft-core processor offers the flexibility to choose or implement a set of features and peripherals that are tailored to the specific application to be developed. An embedded system design model is chosen to act as a framework for the work flow to be carried through the system life cycle starting from the system specification phase and ending with the system release. The developed navigation system is tested first on a mobile robot to reveal system bugs and integration problems, and then on a land vehicle testing platform for further testing. The real-time solution from the implemented system when compared to the solution of a high-end navigation system, proved to be successful in providing a comparable consistent real-time navigation solution. Employing a soft-core processor in the kernel of the navigation system, provided the flexibility for communicating with the various sensors and the computation capability required by the Kalman filter integration algorithm. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2010-10-11 16:08:38.811

Reconfigurable and dynamic computer architecture is an exciting area of research that is rapidly expanding to meet the requirements of compute intense real and non-real time applications in key areas such as cryptography, signal/radar processing and other areas. To meet the demands of such applications, a parallel single-chip heterogeneous Hybrid Data/Command Architecture (HDCA) has been proposed. This single-chip multiprocessor architecture system is reconfigurable at three levels: application, node and processor level. It is currently being developed and experimentally verified via a three phase prototyping process. A first phase prototype with very limited functionality has been developed. This initial prototype was used as a base to make further enhancements to improve functionality and performance resulting in a second phase virtual prototype, which is the subject of this thesis. In the work reported here, major contributions are in further enhancing the functionality of the system by adding additional processors, by making the system reconfigurable at the node level, by enhancing the ability of the system to fork to more than two processes and by designing some more complex real/non-real time applications which make use of and can be used to test and evaluate enhanced and new functionality added to the architecture. A working proof of concept of the architecture is achieved by Hardware Description Language (HDL) based development and use of a Virtual Prototype of the architecture. The Virtual Prototype was used to evaluate the architecture functionality and performance in executing several newly developed example applications. Recommendations are made to further improve the system functionality.

Agile methodologies have become a popular and widely accepted method for managing software development. Since the inception of the Agile Manifesto over ten years ago, agile development techniques have superseded waterfall methods in many, if not most, software development organizations. Despite its apparent success, many companies have struggled with the adoption and implementation of agile, and exactly what level of adoption provides optimum agility. Agility is commonly held in the literature to be constructed of elements external to a company or project but may in fact be composed of both external and internal elements. The exact relationship of the adoption of agile development techniques and their relationship to the actual agility of a business remain unclear. A primary contributor to this uncertainty is the somewhat amorphous definition of agile itself. In academic literature, the concept is still relatively young and loosely defined. In practice, organizations have largely opted for a hybrid approach to agile, mixing its concepts and methods with existing Stage Gate or waterfall methodologies. This has made the management of agile even more complex. Crucially, there is no definition or criterion available to determine the appropriate mix of agile and waterfall processes in an embedded software development context nor is there a method to determine the impact of one against the other. These issues beg the question: how do organizations manage agility? This interpretive case study provides an empirical account of how stakeholders manage both market and process agility in an embedded systems context via a hybrid agility implementation and product genesis. As a result, we provide the notion of agile vorticity, as the point at which market and process agility collide to produce business momentum at a specific point of innovation within the agile business vortex.

Scratch-pad memory is a popular alternative to caches in real-time embedded systems due to its advantages in terms of timing predictability and power consumption. However, dynamic management of scratch-pad content is challenging in multitasking environments. To address this issue, this thesis proposes the design of a novel Real-Time Scratchpad Memory Unit (RSMU). The RSMU can be integrated into existing systems with minimal architectural modi cations. Furthermore, scratchpad management is performed at the OS level, requiring no application changes. In conjunction with a two-level scheduling scheme, the RSMU provides strong timing guarantees to critical tasks. Demonstration and evaluation of the system design is provided on an embedded FPGA platform.

Scratch-pad memory is a popular alternative to caches in real-time embedded systems due to its advantages in terms of timing predictability and power consumption. However, dynamic management of scratch-pad content is challenging in multitasking environments. To address this issue, this thesis proposes the design of a novel Real-Time Scratchpad Memory Unit (RSMU). The RSMU can be integrated into existing systems with minimal architectural modi cations. Furthermore, scratchpad management is performed at the OS level, requiring no application changes. In conjunction with a two-level scheduling scheme, the RSMU provides strong timing guarantees to critical tasks. Demonstration and evaluation of the system design is provided on an embedded FPGA platform.

Security and reliability in processor based systems are concerns requiring adroit solutions. Security is often compromised by code injection attacks, jeopardizing even ???trusted software???. Reliability is of concern, where unintended code is executed in modern processors with ever smaller feature sizes and low voltage swings causing bit flips. Countermeasures by software-only approaches increase code size and therefore significantly reduce performance. Hardware assisted approaches use additional hardware monitors and thus incur considerably high hardware cost and have scalability problems. Considering reliability and security issues during the design of an embedded system has its advantages as this overcomes the limitations of existing solutions. The research work presented in this thesis combines two elements: one, defining a hardware software design framework for reliability and security monitoring at the granularity of micro-instructions, and two, applying this framework for real world problems. At a given time, a processor executes only a few instructions and large part of the processor is idle. Utilizing these idling hardware components by sharing them with the monitoring hardware, to perform security and reliability monitoring reduces the impact of the monitors on hardware cost. Using micro-instruction routines within the machine instructions, allows us to share most of the monitoring hardware. Therefore, our technique requires little hardware overhead in comparison to having additional hardware blocks outside the processor. This reduction in overhead is due to maximal sharing of hardware resources of the processor. Our framework is superior to software-only techniques as the monitoring routines are formed with micro-instructions and therefore reduces code size and execution time overheads, since they occur in parallel with machine instructions. This dissertation makes four significant contributions to the field of security and reliability on embedded processor research and they are: (i) proposed a security and reliability framework for embedded processors that could be included into its design phase; (ii) shown that inline (machine instruction level) monitoring will detect common security attacks (four inline monitors against common attacks cost 9.21% area and 0.67% performance, as opposed to previous work where an external monitor with two monitoring modules costs 15% area overhead); (iii) illustrated that basic block check-summing for code integrity is much simpler and efficient than currently proposed integrity violation detectors which address code injection attacks (this costs 5.03% area increase and 3.67% performance penalty with a single level control flow checking, as opposed to previous work where the area overhead is 5.59%, which needed three control flow levels of integrity checking); and (iv) shown that hardware assisted control flow checking implemented during the design of a processor is much cheaper and effective than software only approaches (this approach costs 0.24-1.47% performance and 3.59% area overheads, as opposed to previous work that costs 53.5-99.5% performance).

Η παρούσα διπλωματική εργασία αναφέρεται στην μέτρηση και την καταγραφή της επιτάχυνσης ενός αντικειμένου. Μετράται η επιτάχυνση και στους τρεις άξονες και η μέτρηση γίνεται μέσω ενός ενσωματωμένου συστήματος, το οποίο είναι βασισμένο στην οικογένεια μίκρο-επεξεργαστών STM32 της εταιρίας ST Microelectronics. Συγκεκριμένα, το σύστημα είναι ο microcontroller STM32-103STK της εταιρίας Olimex, ο οποίος προγραμματίζεται κατάλληλα για τον σκοπό αυτό. Έτσι, αφού περιγραφούν οι ιδιότητες και τα χαρακτηριστικά του προαναφερθέντος συστήματος και των περιφερειακών συσκευών που το πλαισιώνουν, περιγράφονται κάποιες από τις διαθέσιμες σουίτες εφαρμογών που διατίθενται για την ανάπτυξη ενσωματωμένων εφαρμογών. Στην συνέχεια παρουσιάζεται η μεθοδολογία πάνω στην οποία στηρίχθηκε η ανάπτυξη της ενσωματωμένης εφαρμογής. Συγκεκριμένα, ο προγραμματισμός του συστήματος προϋποθέτει την ανά τακτά χρονικά διαστήματα μέτρηση των τιμών επιτάχυνσης στους τρεις άξονες. Οι τιμές αυτές της επιτάχυνσης, αφού εγγραφούν στην οθόνη για να γίνουν ορατές στον χρήστη, αποθηκεύονται σε μία κάρτα τύπου SD (Secure Digital). / This diploma thesis is about measuring and recording an object’s acceleration. The measurement is performed via an embedded system based on the STM32 MCU family made by ST Microelectronics. Specifically the system is the STM32-103STK micro controller made by Olimex. At the beginning of this thesis, the description of the main attributes and features of STM32 processor are stated, and then the available development environments for building and debugging embedded applications. Next the methodology used to develop the embedded application is described. Specifically, the system is programmed to measure the 3-axis applied acceleration and after presenting the values through the monitor, it stores them into a SD (Secure Digital) card.