Distributed heterogeneous embedded systems are increasingly prevalent in numerous applications, including automotive, avionics, smart and connected cities, Internet of Things, etc. With pervasive network access within these systems, security is a critical design concern. This dissertation presents a modeling and optimization framework for distributed, reconfigurable, and heterogeneous embedded systems. Distributed embedded systems consist of numerous interconnected embedded devices, each composed of different computing resources, such single core processors, asymmetric multicore processors, field-programmable gate arrays (FPGAs), and various combinations thereof. A dataflow-based modeling framework for streaming applications integrates models for computational latency, mixed cryptographic implementations for inter-task and intra task communication, security levels, communication latency, and power consumption. For the security model, we present a level-based modeling of cryptographic algorithms using mixed cryptographic implementations, including both symmetric and asymmetric implementations. We utilize a multi-objective genetic optimization algorithm to optimize security and energy consumption subject to latency and minimum security level constraints. The presented methodology is evaluated using a video-based object detection and tracking application and several synthetic benchmarks representing various application types. Experimental results for these design and optimization frameworks demonstrate the benefits of mixed cryptographic algorithm security model compared to single cryptographic algorithm alternatives. We further consider several distributed heterogeneous embedded systems architectures.

Nowadays, more and more embedded systems are equipped with e.g., various sensors that produce large amount of data. One of the challenges of traditional (CPU-based) embedded systems is to process this considerable amount of data such that it produces the appropriate performance level demanded by embedded applications. A solution comes from the usage of a specialized processing unit such as Graphics Processing Unit (GPU). A GPU can process large amount of data thanks to its parallel processing architecture, delivering an im- proved performance outcome compared to CPU. A characteristic of the GPU is that it cannot work alone; the CPU must trigger all its activities. Today, taking advantage of the latest technology breakthrough, we can benefit of the GPU technology in the context of embedded systems by using heterogeneous CPU-GPU embedded systems. Component-based development has demonstrated to be a promising methology in handling software complexity. Through component models, which describe the component specification and their interaction, the methodology has been successfully used in embedded system domain. The existing component models, designed to handle CPU-based embedded systems, face challenges in developing embedded systems with GPU capabilities. For example, current so- lutions realize the communication between components with GPU capabilities via the RAM system. This introduces an undesired overhead that negatively affects the system performance. This Licentiate presents methods and techniques that address the component- based development of embedded systems with GPU capabilities. More concretely, we provide means for component models to explicitly address the GPU-aware component-based development by using specific artifacts. For example, the overhead introduced by the traditional way of communicating via RAM is reduced by inserting automatically generated adapters that facilitate a direct component communication over the GPU memory. Another contribution of the thesis is a component allocation method over the system hardware. The proposed solution offers alternative options in opti- mizing the total system performance and balancing various system properties (e.g., memory usage, GPU load). For the validation part of our proposed solutions, we use an underwater robot demonstrator equipped with GPU hardware. / Ralf 3

In this report the feasibility of using a dual-tag setup in an indoor positioning system was investigated. The reason for the dual-tag setup was to be able to estimate both position and orientation. The system was designed using UWB-technology, with an time of flight trilateration algorithm to calculate the position. The orientation was then estimated from the relative position between the two tags. The system was tested both with stationary tags, but also with the tags moving along two paths. These tests were conducted for different separation distance between the tags, namely 20 cm, 30 cm and 40 cm. The result was that the mean position error for stationary tags was less than 8 cm for all separations and the mean orientation error was less than 3$^\circ$ for all separations. For the moving tag tests a decrease of the error in orientation of about 30 \% could be observed for a separation of 30 and 40 cm compared to 20 cm. However this difference is small in absolute values so more tests are needed to draw any conclusion about whether 30 and 40 cm tag separation performs better than 20 cm tag separation. The performance of the system could also be increased further by optimizing the anchor placement as well as the calibration of the antenna delays of the UWB-modules.

In this master thesis some of the most promising existing frameworks and implementations of deep convolutional neural networks on multiprocessor system-on-chips (MPSoCs) are researched and evaluated. The thesis’ starting point was a previousthesis which evaluated possible deep learning models and frameworks for object detection on infra-red images conducted in the spring of 2018. In order to fit an existing deep convolutional neural network (DCNN) on a Multiple-Processor-System on Chip it needs modifications. Most DCNNs are trained on Graphic processing units (GPUs) with a bit width of 32 bit. This is not optimal for a platform with hard memory constraints such as the MPSoC which means it needs to be shortened. The optimal bit width depends on the network structure and requirements in terms of throughput and accuracy although most of the currently available object detection networks drop significantly when reduced below 6 bits width. After reducing the bit width, the network needs to be quantized and pruned for better memory usage. After quantization it can be implemented using one of many existing frameworks. This thesis focuses on Xilinx CHaiDNN and DNNWeaver V2 though it touches a little on revision, HLS4ML and DNNWeaver V1 as well. In conclusion the implementation of two network models on Xilinx Zynq UltraScale+ ZCU102 using CHaiDNN were evaluated. Conversion of existing network were done and quantization tested though not fully working. The results were a two to six times more power efficient implementation in comparison to GPU inference.

O aumento da complexidade dos sistemas embarcados e a necessidade de um desenvolvimento cada vez mais acelerado têm motivado o uso de modelos abstratos que possibilitem maior flexibilidade e reusabilidade. Para isso, faz-se necessária a aceitação das linguagens e perfis mais abstratos, como o MARTE. Neste trabalho, foi desenvolvida uma ferramenta para conversão de sistemas embarcados independente de plataforma (PIM) em sistemas de uma plataforma específica (PSM), denominada I2S (Independente to Specific). O I2S é totalmente acoplável a novos desenvolvimentos e necessidades do projetista, capaz de modelar representações gráficas de sistemas embarcados, usando componentes do MARTE e permitindo uma implementação final em tecnologia reconfigurável. A partir de um modelo independente de plataforma faz-se a conversão para o padrão de projeto SOPC-Builder da Altera e XPS da Xilinx, possibilitando a exploração do espaço de projeto nessas duas tecnologias de modo automático. O trabalho faz análise de sistemas convertidos em diversas configurações e traz resultados relevantes para a área que validam o uso da proposta, atendendo aos requisitos de projeto / The growing of embedded systems complexity and the want for a quicker development has motivated the use of abstract models that improves flexibility and reusability. To these objective, we searched for the most adequate languages and profiles, like MARTE. In this work we developed a tool for conversion from platform independent models (PIM) to platfom specific models (PSM), named I2S (Independent to Specific). The I2S is totally acceptable to new developments and necessities of the designer, to open up modelling graphic representations of embedded systems using MARTE components and doing implementation in reconfigurable technology. A platform independent model is converted to the pattern of Alteras SOPC-Builder and Xilinxs XPS, making possible the exploitation of the project space in theses two tecnologies automatically. The work does analysis of systems converted in different configurations and shows relevant results to the area that validate the use of the proposal, meeting the project requirements

O contínuo avanço da capacidade dos circuitos integrados e a necessidade de sistemas embarcados cada vez mais complexos para lidar com os problemas atuais, com prazos cada vez mais curtos, estão direcionando o desenvolvimento de sistemas de circuitos integrados para ambientes de alto nível de abstração cada vez mais distantes dos detalhes de hardware. O uso de linguagens de alto nível para auxiliar o desenvolvimento de sistemas embarcados é uma tendência atual pois tal abordagem tende a reduzir a complexidade e o tempo de desenvolvimento. Este trabalho propõe o desenvolvimento de uma nova ferramenta para geração de arquiteturas de hardware em Bluespec em um ambiente gráfico utilizando diagramas da UML. Esta ferramenta permite que o projetista descreva o comportamento utilizando máquina de estados finita no padrão UML 2.0, onde cada estado pode conter a codificação do comportamento com as linguagens Bluespec e C. Dada uma máquina de estados, a mesma é traduzida para a linguagem Bluespec por meio de um compilador e templates. Como resultado, é apresentado a geração de duas arquiteturas de hardware a fim de demonstrar as vantagens e limitações da ferramenta desenvolvida / The continuous advancement of integrated circuits capacity and the need for embedded systems even more complex to deal with current problems, with shorter time-to-market, are driving the development of integrated circuits systems to environments with high level abstraction more and more distant from the hardware details. The use of high level languages to assist the embedded systems development is a current trend for such an approach tends to reduce the complexity and development time. This work proposes the development of a new tool in Bluespec to generate hardware architectures in a graphical environment using UML diagrams. This tool allows the designer to describe the behavior using finite state machine in UML 2.0 standard, where each state can contain the coding behavior with Bluespec and C languages. Given a state machine, it is translated to Bluespec language through a compiler and templates. As a result is presented the generation of two hardware architectures in order to demonstrate the advantages and limitations of the developed tool

Demand of CO2 gas sensors is expected to continue to increase in the foreseeable future, due to an increasing awareness of air pollution and fossil fuel emissions. A truly low cost and accurate NDIR sensor has the potential of greatly benefiting the environment by an increased human awareness due to CO2 measurements. In the objective to reach these goals, a CO2 sensor core on an ASIC needs to be investigated. In this study an ASIC prototype design is tested on an FPGA and evaluated towards logic resource requirements, power analysis and estimated cost impacts towards a full ASIC. The results show that a potential ASIC implementation would have a very small cost impact on a full system design if the use of a preexisting ASIC design is utilized. Using a manufacturing process of 180 nm, the total logic implementation would require between 0.54-0.76 mm2. The cost impact of such a logic area would be around $0.025 USD per chip. The power consumption of the logical part would also be very small when compared to the various analog components of a full system design.

Le diabète de type 1 est une maladie immune caractérisée par la destruction des cellules béta du pancréas responsable de la production de l’insuline, l’hormone qui joue un rôle primordial dans la régulation du glucose sanguin. Les patients diabétiques de type 1 font face tous les jours à un problème d’optimisation puisqu’ils doivent s’injecter des doses optimales d’insuline durant toute la journée. Une des perturbations majeure du contrôle de glucose est l’activité physique. Malgré les bénéfices, l’exercice est généralement associé à un risque accru de faibles niveaux de glucose. La crainte de l’hypoglycémie résulte soit en l’évitement total de l’exercice physique ou en une surdose lors de compensation au niveau du traitement à l’insuline ce qui mène à un pire contrôle métabolique.Cette dissertation a pour objectif de permettre aux patients diabétiques de type 1 de s’engager dans une activité physique en informant en temps réel sur le risque associé à l’exercice et en recommandant des ajustements des doses d’insulines et de glucides.Des modèles statistiques linéaires ont été la base dans la conception et implémentation d’un système d’aide à la décision permettant aux diabétiques de type 1 de minimiser les risques associés à l’activité physique. Ce système contient des stratégies optimales pour réduire les épisodes hypoglycémiques suivant l’exercice. Le système a été évalué et validé à l’aide du simulateur de diabète de type 1 créé par Université de Virginie/Université de Padoue et sera déployé dans des essais cliniques dans le futur proche. / Type1 diabetes (T1D) is an immune disease characterized by the destruction of the beta cells of the pancreas responsible for the production of insulin, a hormone that plays a primary role in blood glucose regulation. People with T1D are faced with daily challenges of optimization since they require multiple daily infusions of optimal insulin doses. One of the major disturbances of glycemic control is physical activity. Despite its benefits, exercise is usually associated with higher risks of low glucose levels. The fear of hypoglycemia results in either avoidance of engaging in a physical activity or over- compensatory treatment behaviors that lead to a worse metabolic control.This dissertation project focuses on enabling physical activity for T1DM patients by generating real time feedback of the current risks associated with exercise and advising on insulin dose adjustments and carbohydrate intakes.Using linear statistics techniques, we identified the major factors predictive of the post exercise glycemic response in a relatively large dataset of T1D patients. Based on this analysis, we developed a classification method able to warn T1D patients in advance of a high risk for hypoglycemia associated with physical activity, potentially allowing patients to delay exercise or take preventive actions.The linear statistical models were the foundation in the design and implementation of a decision support system (DSS) for people with T1D to safely engage in a physicalactivity. The DSS has built-in optimized strategies to mitigate the risk of exercise- induced low glucose levels. The system has been validated in the University of Virginia/University of Padova FDA approved T1D simulator and will be deployed in clinical trials in the near future.

Técnicas que partem de modelos de alto nível de abstração são requeridas para lidar com a complexidade encontrada nas novas gerações de sistemas embarcados, sendo cruciais para o sucesso do projeto. Uma grande redução do esforço pode ser obtida com o uso de modelos quando código em uma linguagem de programação pode ser gerado automaticamente a partir desses. Porém, ferramentas disponíveis para modelagem e geração de código normalmente são dependentes de domínio e o software embarcado normalmente possui comportamento heterogêneo, requerendo suporte a múltiplos modelos de computação. Nesta tese, estratégias para desenvolvimento de software embarcado baseado em modelos de alto nível usando UML e Simulink são analisadas. A partir desta análise, observaram-se as principais limitações das abordagens para geração de código baseadas em UML e Simulink. Esta tese, então, propõe estratégias para melhorar a automação provida por estas ferramentas, como por exemplo, propondo uma abordagem para geração de código multithread a partir de modelos Simulink. A comparação feita entre UML e Simulink mostra que, embora UML seja a linguagem mais usada no domínio de engenharia de software, UML é baseada em eventos e não é adequada para modelar sistemas dataflow. Por outro lado, Simulink é largamente usado por engenheiros de hardware e de controle, além de suportar dataflow e geração de código. Porém, Simulink provê abstrações de mais baixo nível, quando comparado a UML. Conclui-se que tanto UML como Simulink possuem prós e contras, o que motiva a integração de ambas linguagens em um único fluxo de projeto. Neste contexto, esta tese propõe também uma abordagem integradora para desenvolvimento de software embarcado que inicia com uma especificação de alto nível descrita usando diagramas UML, a partir da qual modelos dataflow e control-flow podem ser gerados. Desta maneira, o modelo UML pode ser usado como front-end para diferentes abordagens de geração de código, incluindo UML e a proposta geração de código multithread a partir de modelos Simulink. / The use of techniques starting from higher abstraction levels is required to cope with the complexity that is found in the new generations of embedded systems, being crucial to the design success. A large reduction of design effort when using models in the development can be achieved when there is a possibility to automatically generate code from them. Using these techniques, the designer specifies the system model using some abstraction and code in a programming language is generated from that. However, available tools for modeling and code generation are domain-specific and embedded software usually shows heterogeneous behavior, which pushes the need for supporting software automation under different models of computation. In this thesis, strategies for embedded software development based on high-level models using UML and Simulink were analyzed. We observed that the embedded software generation approaches based on UML and Simulink have limitations, and hence this thesis proposes strategies to improve the automation provided on those approaches, for example, proposing a Simulink-based multithread code generation. UML is a well used language in the software engineering domain, and we consider that it has several advantages. However, UML is event-based and not suitable to model dataflow systems. On the other side, Simulink is widely used by control and hardware engineers and supports dataflow, and time-continuous models. Moreover, tools are available to generate code from a Simulink model. However, Simulink models represent lower abstraction level compared to UML ones. This comparison shows that UML and Simulink have pros and cons, which motivates the integration of both languages in a single design process. As the main contribution, we propose in this thesis an integrated approach to embedded software design, which starts from a high-level specification using UML diagrams. Both dataflow and control-flow models can be generated from that. In this way, an UML model can be used as front-end for different code generation approaches, including UML-based one and the proposed Simulink-based multithread code generation.

Atualmente, a adição de uma nova função implementada em hardware em um processador não deve impor nenhuma mudança no conjunto de instruções (ISA – Instruction Set Architecture) suportado para atingir melhorias em seu desempenho. O objetivo é manter a compatibilidade retroativa e futura de programas já compilados. Todavia, este fato se torna, muitas vezes, um fator impeditivo para o aprimoramento ou desenvolvimento de uma nova arquitetura. Desta maneira, a utilização de mecanismos de Tradução Binária abre novas oportunidades aos projetistas, já que estes mecanismos permitem a execução de programas já compilados em arquiteturas que suportam conjuntos de instruções diferentes do previsto inicialmente. Assim, para eliminar o custo adicional apresentado por estes sistemas de tradução, será proposto um novo mecanismo de tradução binária dinâmico de dois níveis. Enquanto o primeiro nível é responsável pela tradução de facto das instruções do conjunto nativo para instruções de uma linguagem de máquina intermediária, o segundo nível otimiza estas instruções já traduzidas para serem executadas na arquitetura alvo. O sistema é totalmente flexível, pois pode suportar a tradução de conjuntos de instruções completamente diferentes; assim como a utilização de arquiteturas de hardware com as mais diversas características. Este trabalho apresenta o primeiro esforço nesta direção: um estudo de caso onde ocorre a tradução de código x86 para MIPS (linguagem intermediária), que será otimizado para ser executado em uma arquitetura que realiza reconfiguração dinâmica. Resta demonstrado que é possível manter a compatibilidade binária, com melhoria no desempenho em torno de 45% em média e consumo de energia semelhante ao da execução nativa. / In these days, every new added hardware feature must not change the underlying instruction set architecture (ISA), in order to avoid adaptation or recompilation of existing code. Therefore, Binary Translation (BT) opens new possibilities for designers, previously tied to a specific ISA and all its legacy hardware issues, since it allows the execution of already compiled applications on different architectures. To overcome the BT inherent performance penalty, we propose a new mechanism based on a dynamic two-level binary translation system. While the first level is responsible for the BT de facto to an intermediate machine language, the second level optimizes the already translated instructions to be executed on the target architecture. The system is totally flexible, supporting the porting of radically different ISAs and the employment of different target architectures. This work presents the first effort towards this direction: it translates code implemented in the x86 ISA to MIPS assembly (the intermediate language), which will be optimized by the target architecture: a dynamically reconfigurable architecture. In this work is showed that is possible to maintain binary compatibility with performance improvements on average 45% and similar energy consumption when compared to native execution.