Esta dissertação propõe a utilização da técnica de filtragem adaptativa de pulsos transientes de modo a proteger os circuitos integrados sob efeito da radiação ionizante. Para garantir o uso desta técnica é necessária a utilização de um flip-flop tolerante à radiação que possua a capacidade de ter um ajuste de atraso configurável. O objetivo do uso do flip-flop programável é ter a opção de selecionar o atraso mais apropriado para filtragem temporal de pulsos de SET para cada circuito. Sendo assim, cada flip-flop pode filtrar SETs pelo uso de diferentes atrasos, baseado no atraso de propagação de cada caminho lógico. A variação nos atrasos de propagação entre múltiplos caminhos combinacionais pode ser usada para aumentar ou reduzir o atraso da filtragem de SET. Esta abordagem foi validada com o estudo de caso através de simulação elétrica e pela injeção de milhares de pulsos de SET com diferentes larguras em um circuito com filtragem adaptativa de pulsos tolerantes, os quais foram injetados de forma randômica no circuito. Os resultados mostraram o uso eficiente desta técnica de filtragem de SET em circuitos integrados. De modo a maximizar os resultados, um novo elemento de atraso programável foi desenvolvido e inserido no flip-flop. Para validação deste novo elemento, um segundo estudo de caso, utilizando o conjunto de circuitos dos benchmarks do ISCAS'85 foi também avaliado com a injeção de falhas. Os resultados mostraram que o uso do método proposto, reduz o número de erros sem perda de desempenho e com baixo incremento de área. / This dissertation proposes the use of an adaptive filtering technique of transient pulses in order to protect the integrated circuit under the effect of radiation. To ensure this technique it is necessary to use a tolerant radiation flip-flop having the ability to have a configurable delay adjustment. The purpose of the use a programmable radiation hardened flip-flop is having option of to select the most appropriate delay in the SET temporal filtering for each flip-flop in a circuit. Thus, each flip-flop can filter SETs by using different delays based on the propagation-delay of its logical path. The propagation-delay variances among multiple paths can be used to increase or reduce the delay of the SET filtering. This approach was validated in a case-study by electrical simulation with injection of thousands of SET pulses of different widths, which were randomly injected in a circuit with adaptive filtering technique and the results showed efficient use of this SET filtering technique in integrated circuits. In order to maximize the results of this technique a new programmable delay element was developed and inserted into the flip-flop. This approach of the new element was validated in a second case-study, using a set of benchmark circuits from ISCAS’85 was also evaluated by injecting faults. Results showed that using the proposed method, the number of errors can be reduced without decreasing the performance and with low area overhead.

A diminuição no tamanho dos dispositivos nas tecnologias do futuro traz consigo um grande aumento na taxa de erros dos circuitos, na lógica combinacional e seqüencial. Apesar de algumas potenciais soluções começarem a ser investigadas pela comunidade, a busca por circuitos tolerantes a erros induzidos por radiação, sem penalidades no desempenho, área ou potência, ainda é um assunto de pesquisa em aberto. Este trabalho propõe duas soluções para lidar com este comportamento imprevisível das tecnologias futuras: a primeira solução, chamada MemProc, é uma arquitetura baseada em memória que propõe reduzir a taxa de falhas de aplicações embarcadas micro-controladas. Esta solução baseia-se no uso de memórias magnéticas, que são tolerantes a falhas induzidas por radiação, e área de circuito combinacional reduzida para melhorar a confiabilidade ao processar quaisquer aplicações. A segunda solução proposta aqui é uma implementação de um IP de infra-estrutura para o processador MIPS indicada para sistemas em chip confiáveis, devido a sua adaptação rápida e por permitir diferentes níveis de robustez para a aplicação. A segunda solução é também indicada para sistemas em que nem o hardware nem o software podem ser modificados. Os resultados dos experimentos mostram que ambas as soluções melhoram a confiabilidade do sistema que fazem parte com custos aceitáveis e até, no caso da MemProc, melhora o desempenho da aplicação. / Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions are being investigated by the community, the search for circuits tolerant to radiation induced errors, without performance, area, or power penalties, is still an open research issue. This work proposes two solutions to cope with this unpredictable behavior of future technologies: the first solution, called MemProc, is a memory based architecture proposed to reduce the fault rate of embedded microcontrolled applications. This solution relies in the use magnetic memories, which are tolerant to radiation induced failures, and reduced combinational circuit area to improve the reliability when processing any application. The second solution proposed here is an infrastructure IP implementation for the MIPS architecture indicated for reliable systems-on-chip due to its fast adaptation and different levels of application hardening that are allowed. The second solution is also indicated for systems where neither the hardware nor the software can be modified. The experimental results show that both solutions improve the reliability of the system they take part with affordable overheads and even, as in the case of the MemProc solution, improving the performance results.

Esta dissertação propõe a utilização da técnica de filtragem adaptativa de pulsos transientes de modo a proteger os circuitos integrados sob efeito da radiação ionizante. Para garantir o uso desta técnica é necessária a utilização de um flip-flop tolerante à radiação que possua a capacidade de ter um ajuste de atraso configurável. O objetivo do uso do flip-flop programável é ter a opção de selecionar o atraso mais apropriado para filtragem temporal de pulsos de SET para cada circuito. Sendo assim, cada flip-flop pode filtrar SETs pelo uso de diferentes atrasos, baseado no atraso de propagação de cada caminho lógico. A variação nos atrasos de propagação entre múltiplos caminhos combinacionais pode ser usada para aumentar ou reduzir o atraso da filtragem de SET. Esta abordagem foi validada com o estudo de caso através de simulação elétrica e pela injeção de milhares de pulsos de SET com diferentes larguras em um circuito com filtragem adaptativa de pulsos tolerantes, os quais foram injetados de forma randômica no circuito. Os resultados mostraram o uso eficiente desta técnica de filtragem de SET em circuitos integrados. De modo a maximizar os resultados, um novo elemento de atraso programável foi desenvolvido e inserido no flip-flop. Para validação deste novo elemento, um segundo estudo de caso, utilizando o conjunto de circuitos dos benchmarks do ISCAS'85 foi também avaliado com a injeção de falhas. Os resultados mostraram que o uso do método proposto, reduz o número de erros sem perda de desempenho e com baixo incremento de área. / This dissertation proposes the use of an adaptive filtering technique of transient pulses in order to protect the integrated circuit under the effect of radiation. To ensure this technique it is necessary to use a tolerant radiation flip-flop having the ability to have a configurable delay adjustment. The purpose of the use a programmable radiation hardened flip-flop is having option of to select the most appropriate delay in the SET temporal filtering for each flip-flop in a circuit. Thus, each flip-flop can filter SETs by using different delays based on the propagation-delay of its logical path. The propagation-delay variances among multiple paths can be used to increase or reduce the delay of the SET filtering. This approach was validated in a case-study by electrical simulation with injection of thousands of SET pulses of different widths, which were randomly injected in a circuit with adaptive filtering technique and the results showed efficient use of this SET filtering technique in integrated circuits. In order to maximize the results of this technique a new programmable delay element was developed and inserted into the flip-flop. This approach of the new element was validated in a second case-study, using a set of benchmark circuits from ISCAS’85 was also evaluated by injecting faults. Results showed that using the proposed method, the number of errors can be reduced without decreasing the performance and with low area overhead.

Cooperative Impulse Response – Ultra Wideband (IR-UWB) communication is a radio technology very popular for short range communication systems as it enables single-antenna mobiles in a multi-user environment to share their antennas by creating virtual MIMO to achieve transmit diversity. In order to improve the cooperative IR-UWB system performance, we are going to use Differential Code Shifted Reference (DCSR). The simulations are used to compute Bit Error Rate (BER) of DCSR in cooperative IR-UWB system using different numbers of Decode and Forward relays while changing the distance between the source node and destination nodes. The results suggest that when compared to Code Shifted Reference (CSR) cooperative IR-UWB communication system; the DCSR cooperative IR-UWB communication system performs better in terms of BER, power efficiency and channel capacity. The simulations are performed for both non-line of sight (N-LOS) and line of sight (LOS) conditions and the results confirm that system has better performance under LOS channel environment. The simulation results also show that performance improves as we increase the number of relay nodes to a sufficiently large number. / +923214674079 , +923234155044

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Master’s thesis engages in the impact of polarization mode dispersion on optical communication system. Polarization mode dispersion is mathematically described by Stoke’s and Jone’s space and ensure the theoretic causes of the rise of polarization mode dispersion that are divided on the external and internal effects. On the basis of these effects grow up a differential group delay (DGD) which makes causes that individual polarization modes have between them a time delay and limitation of maximum bit rate. Then master´s thesis analyses the influence of the polarization mode dispersion on the pulse enlargement and on the modulation signal. In this work, there are described the most applicated optical modulation formats. Polarization mode dispersion has also influence on the bit error rate of optical fibre link and closing of eye diagram too. Eye diagram is used to view the transmission characteristics and diagnoses the channel errors. Eye diagram is connected with the definitions as a bit error rate (BER) and signal-to-noise ratio (SNR) that are explained in this work too. Following the gained experiences it was designed an useful graphic interface to display the effect of the polarization mode dispersion on the transmitted signal. Realization of the graphic interface is created in the program MATLAB. In Matlab-Simulink are created six models according to the kind of modulations with characteristic AWGN (Additive White Gaussian Noise) channel. Program was tested for a typical values. In all calculations it is counted only with the losses that are caused by the polarization mode dispersion. It is not calculated with the losses that are caused by a chromatic dispersion and attenuation. At the end of this work are evaluated all types of modulation formats depending on the polarization mode dispersion, optical fibre length, price and complexity of the realization. Atteined results of my master’s thesis are compared with two foreign articles.

The master‘s thesis is focused on data transfer over power lines. The influence of connected devices on data signal is studied. In this thesis, you can find the descriptions of PLC technology characteristics, sources of signal interruption and, mainly, the method of modelling the PLC channels as a multipath signal propagation environment is thoroughly discussed. There are models of PLC channels using this method projected in Simulink. The analysis of the influence of connected devices to bit error rate of a signal is processed. The devices are modelled by connected impedance.

This work is dealing with the design of intermediate part of transmitter and reciever that use digital BPSK and QPSK modulations for microwave link that works in 24 – 26 GHz bands. Besides choosing the suitable modulator and demodulator there was need to provide proper connection of this part with transceiver Nortel CTR26-01M. Input and output of this intermediate part was take out to baseband, where was need to ensure the transfer of diferential inputs of modulator and demodulator to symetric leading for reason of data communication with PC, for which was created the algorithms to provide transmitting and receiving data. Complete structure controlled by the microcontroller has been enliven and furthemore there was created the measurement of chosen parameteres.

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