Dissertation (Ph.D.)--Auburn University, 2005. / Vita. Includes bibliographical references (ℓ. 79-83).

Dissertation (Ph.D.)--Auburn University, 2005. / Abstract. Vita. Includes bibliographic references.

Zugl.: Berlin, Humboldt-Univ., Diss., 2007

Techn. Universiẗat, Diss., 2005--Berlin.

The demand for high performance microelectronic products drives the development of 3-D chip-stacking structure. By the introduction of through-silicon-via (TSV) into 3-D flip-chip packages, microelectronic performance is improved by increasing circuit capacity and diminishing signal delay. However, TSV-embedded structure also raises concerns over many reliability issues that come with the steep thermal and mechanical transient responses, increasing numbers of bi-material interfaces and reduced component sizes. In this research, defect initiation induced by thermalmechanical phenomena is studied to establish the early failure modes within 3-D flip-chip packages. It is found that low amplitude but extremely high frequency thermal stress waves would occur and attenuate rapidly in the first hundreds of nanoseconds upon power-on. Although the amplitude of these waves is far below material yielding points, their intrinsic characteristics of high frequency and high power density are capable of compromising the integrity of all flip-chip components. By conducting spectral analysis of the stress waves and applying the methodology of accumulated damage evaluation, it is demonstrated that micron crack initiation and interconnect debond are highly probable in the immediate proximity of the heat source. Such a negative impact exerted by the stress wave in the early, while brief, transient period is recognized as the short time scale dynamic effect. Researched results strongly indicate that short-time scale effects would inflict very serious reliability issues in 3-D flip-chip packages. The fact that 3-D flip-chip packages accommodate a large amount of reduced-size interconnects makes it vulnerable to the attack of short time scale propagating stress waves. In addition, the stacking structure also renders shearing effect extremely detrimental to 3-D flip-chip integrity. Finally, several guidelines effective in discouraging short-time scale effects and thus improving TSV flip-chip package reliability are proposed

As the trend of miniaturization of complex integrated circuit(IC) devices, the current density of flip-chip solder bumps have increased significantly and each solder joint is supporting a current density close to or even over 104 A/cm2 .Therefore, in SnPb eutectic solder, which has a high diffusivity at the operating temperature due to its low melting point, the electromigration becomes a major reliability threat. Thus, the thesis is aimed to investigate the effects of electromigration behavior on flip-chip package eutectic Sn-Pb solder bumps reliability under high current density. The current densities are 2x104 A/cm2 and 1.5x104 A/cm2,the surface of die temperatures are 115¢Jand 95¢J.The bump temperature, the histories of the bump resistance, and mean time to failure (MTTF) testings were conducted. The failure mechanism was observed through SEM and EDS. From the results of the experiment, the dominant failure mode of the bump is due to electromigration behavior that causes voids at UBM/bump interface (cathode) when the sample¡¦s failure time is shorter. As the failure time is longer, the failure is also resulted from heat effect in addition to electromigration behavior.

Abstract Accompany a rapid growth in the semiconductor industry in the past few year, most components gradually used the small dimension as its basic structures. Due to the reduction of component size will induces highly concentrated on circuit and dimension, it also incurs a lots problem, such as electromagnetic interference, high temperature and thermal stress, which will decrease the product reliability. The most common damage in the semiconductor product is thermal fatigue, which is caused by thermal stress concentrated under repeatedly temperature variation loading. Usually, the thermal cycle loading is applied to induce the fatigue destruction and predict the product reliability, but this method spends one cycle for 80min which is time-consumption. Therefore, in this thesis, the finite element method package is used to simulate and evaluate the plastic variation of solder bump and the relation between different temperatures loading and equivalent plastic strain under different temperature range test. Through the Coffin-Manson equation, the equivalent plastic strain can be used to predict the fatigue live, which can be precisely accelerating the fatigue test.

The trend of electrical products is light, thin and minimized with the fast operation and multi functionality, which also drives assembly technology towards the same goal. In advanced assembly technology, flip-chip is the one that can achieve the purposes. The pitch and size of a bump, which is in charge of current transmit, are also getting small. The prohibition of using lead content material also stimulates the development of lead-free material in the related industries. The paper is focused on adopting lead free solder paste such as Sn/Ag1.0/Cu0.5 and Sn/Ag4.0/Cu0.5, together with Al/NiV/Cu UBM made by bumping technology. The empirical analysis is based the shear strength of three different bump heights. The result shows the higher the content of Ag, the higher of the initial shear strength. Moreover, the experiment also investigated two solder bump IMC conditions and shear strength by using multi-reflow. The result shows that the IMC of Sn/Ag4.0/Cu0.5 solder paste increases after times of multi-reflow, but the shear strength was sharply decreased. The reliability test was also performed, such as temperature cycling test, temperature and humidity test, highly accelerated temperature and humidity stress test, high temperature storage life test. It¡¦s found the Sn/Ag1.0/Cu0.5 solder bump could maintain the original ductility; while the Sn/Ag4.0/Cu0.5 solder bump was decreasing the ductility due to the generation of IMC. Keyword¡GShear Strength, Flip-chip, Bump, IMC

We have fabricated a laser array module using a passive self-aligned flip-chip bonding technique. Silicon optical bench was used as a submount with PbSn (Tm=183¢J) solder bump and V-grooves. A 4-channel laser array was flip-chip mounted with coupling efficiency of 56% to cleaved 62.5/125£gm multimode fiber ribbons. The optimum fabrication parameters were bonding time of 20 seconds and bonding load of 10g. The average misalignments were measured to be 1£gm and 5£gm for X and Y directions , respectively.

Thesis (M.S.)--Mechanical Engineering, Georgia Institute of Technology, 2004. / Daniel Baldwin, Committee Chair; Suresh Sitaraman, Committee Member; Steven Danyluk, Committee Member. Includes bibliographical references (leaves 238-241).