The subject of this paper is to the research and develop Liquid Crystal Display Module(LCM) test system for LCM factories.We prpose an FPGA,built in an NiosII soft CPU,as the control core with peripheral circuits to form a flexible SOPC¡]System on Programmable Chip¡^. Using this digital circuit being synthetic with the hardware description language, one can further integrate analog and digital peripheral devices by software control to establish a universal of medium and small LCM tester, and can conduct display function verification on such system. This system has been proved effectively to perform functional test for multi type LCM, and meanwhile it further demonstrates the advantage in its flexibility for configuration change due to its SOPC design.

This research is focused on identifying an appropriate design for a reconfigurable Body Area Network (BAN). In order to investigate the benefits and drawbacks of the proposed design, a BAN system prototype was built. This system consists of two distinct node types: a slave node and a master node. These nodes communicate using ZigBee radio transceivers. The microcontroller-based slave node acquires sensor data and transmits digitized samples to the master node. The master node is FPGA-based and runs uClinux on a soft-core microcontroller. The purpose of the master node is to receive, process and store digitized sensor data. In order to verify the operation of the BAN system prototype and demonstrate reconfigurability, a specific application was required. Pattern recognition in electrocardiogram (ECG) data was the application used in this work and the MIT-BIH Arrhythmia Database was used as the known data source for verification. A custom test platform was designed and built for the purpose of injecting data from the MIT-BIH Arrhythmia Database into the BAN system. The BAN system designed and built in this work demonstrates the ability to record raw ECG data, detect R-peaks, calculate and record R-R intervals, detect premature ventricular and atrial contractions. As this thesis will identify, many aspects of this BAN system were designed to be highly reconfigurable allowing it to be used for a wide range of BAN applications, in addition to pattern recognition of ECG data.

A physical control/protection platform needs to be tested and its functionality verified prior to installation and commissioning. Closed-loop testing of a physical control/protection platform, in a real-time simulator environment is practically the only option to safely and thoroughly verify the design integrity and evaluate its functionality and performance. Moreover, a real-time simulator is also required to conduct statistical switching studies, as it substantially reduces the total run time of the study. This thesis proposes and develops a generalized methodology for implementation of the power system equations in the FPGA environment. The developed methodology enables real-time operation, for closed-loop testing of physical control/protection platforms in hardware-in-the-loop (HIL) configuration, and even faster-than-real-time operation, for statistical switching studies. Based on the developed methodology, an FPGA-based simulator is developed and tested. The salient features of the proposed implementation are: ² It enables the use of a nanosecond range simulation time-step to simulate large systems in real-time, in contrast to the us range time-steps used in the existing simulators. Thus it is also able to provide a wide frequency bandwidth for the simulation results. ² It retains the calculation time, within each simulation time-step, nearly fixed irrespective of the size of the system. ² It eliminates the need for the corrective measures, adopted in the existing real-time simulators, to reduce error due to the lack of synchronization between the simulation time-grid and the output signals of the control/protection platform under test. As an integral part of this work, this thesis proposes and develops the modified two-layer network equivalent (M-TLNE). The salient feature of the M-TLNE is its computational efficiency, as compared to the existing network equivalents, which makes it a prime choice for statistical switching studies and real-time simulation of electromagnetic transients. This thesis also proposes a generalized methodology, applicable to both single and multi-port network equivalents for both single- and multi-phase systems, for developing the proposed M-TLNE. The developed methodology ensures the stability and passivity of the M-TLNE.

This thesis presents two contributions to the FPGA CAD domain. First, a study of glitch power in a commercial FPGA is presented, showing that glitch power in FPGAs is significant. A CAD algorithm is presented that reduces glitch power at the post-routing stage by taking advantage of don't-cares in the logic functions of the circuit. This method comes at no cost to area or performance. The second contribution of this thesis is a study of FPGA CAD algorithm noise {random choices which can have an unpredictable effect on the circuit as a whole. An analysis of noise in the logic synthesis, technology mapping, and placement stages is presented. A series of early performance and power metrics is proposed, in an effort to find the best circuit implementation in the noise space.

With the availability of multi-core processors, high capacity FPGAs, and GPUs, a heterogeneous platform with tremendous raw computing capacity can be constructed consisting of any number of these computing elements. However, one of the major challenges for constructing such a platform is the lack of a standardized framework under which an application’s computational task and data can be easily and effectively managed amongst the computing elements. In this thesis work such a framework is developed based on OpenCL (Open Computing Language). An OpenCL API and run time framework, called O4F, was implemented to incorporate FPGAs in a platform with CPUs and GPUs under the OpenCL framework. O4F help explore the possibility of using OpenCL as the framework to incorporate FPGAs with CPUs and GPUs. This thesis details the findings of this first-generation implementation and provides recommendations for future work.

The object detection framework developed by Viola and Jones has become very popular due to its high quality and detection speed. However, the complexity of the computation required to train a detector makes it difficult to develop and test potential improvements to this algorithm or train detectors in the field. In this thesis, a configurable, high-performance FPGA architecture is presented to accelerate this training process. The architecture, structured as a systolic array of pipelined compute engines, is constructed to provide high throughput and make efficient use of the available external memory bandwidth. Extensions to the Viola-Jones detection framework are implemented to demonstrate the flexibility of the architecture. The design is implemented on a Xilinx ML605 development platform running at 200~MHz and obtains a 15-fold speed-up over a multi-threaded OpenCV implementation running on a high-end processor.

This thesis presents two contributions to the FPGA CAD domain. First, a study of glitch power in a commercial FPGA is presented, showing that glitch power in FPGAs is significant. A CAD algorithm is presented that reduces glitch power at the post-routing stage by taking advantage of don't-cares in the logic functions of the circuit. This method comes at no cost to area or performance. The second contribution of this thesis is a study of FPGA CAD algorithm noise {random choices which can have an unpredictable effect on the circuit as a whole. An analysis of noise in the logic synthesis, technology mapping, and placement stages is presented. A series of early performance and power metrics is proposed, in an effort to find the best circuit implementation in the noise space.

With the availability of multi-core processors, high capacity FPGAs, and GPUs, a heterogeneous platform with tremendous raw computing capacity can be constructed consisting of any number of these computing elements. However, one of the major challenges for constructing such a platform is the lack of a standardized framework under which an application’s computational task and data can be easily and effectively managed amongst the computing elements. In this thesis work such a framework is developed based on OpenCL (Open Computing Language). An OpenCL API and run time framework, called O4F, was implemented to incorporate FPGAs in a platform with CPUs and GPUs under the OpenCL framework. O4F help explore the possibility of using OpenCL as the framework to incorporate FPGAs with CPUs and GPUs. This thesis details the findings of this first-generation implementation and provides recommendations for future work.

The object detection framework developed by Viola and Jones has become very popular due to its high quality and detection speed. However, the complexity of the computation required to train a detector makes it difficult to develop and test potential improvements to this algorithm or train detectors in the field. In this thesis, a configurable, high-performance FPGA architecture is presented to accelerate this training process. The architecture, structured as a systolic array of pipelined compute engines, is constructed to provide high throughput and make efficient use of the available external memory bandwidth. Extensions to the Viola-Jones detection framework are implemented to demonstrate the flexibility of the architecture. The design is implemented on a Xilinx ML605 development platform running at 200~MHz and obtains a 15-fold speed-up over a multi-threaded OpenCV implementation running on a high-end processor.

Difficulties and dangers in doing experiments on living systems and providing a testbed for theorists make the biologically detailed neural simulation an essential part of neurobiology. Due to the complexity of the neural systems and dynamic properties of the neurons simulation of biologically realistic models is very challenging area. Currently all general purpose simulator are software based. Limitation on the available processing power provides a huge gap between the maximum practical simulation size and human brain simulation as the most complex neural system. This thesis aimed at providing a hardware friendly parallel architecture in order to accelerate the simulation process.<p> This thesis presents a scalable hierarchical architecture for accelerating simulations of large-scale biological neural systems on field-programmable gate arrays (FPGAs). The architecture provides a high degree of flexibility to optimize the parallelization ratio based on available hardware resources and model specifications such as complexity of dendritic trees. The whole design is based on three types of customized processors and a switching module. An addressing scheme is developed which allows flexible integration of various combination of processors. The proposed addressing scheme, design modularity and data process localization allow the whole system to extend over multiple FPGA platforms to simulate a very large biological neural system.<p> In this research Hodgkin-Huxley model is adopted for cell excitability. Passive compartmental approach is used to model dendritic tree with any level of complexity. The whole architecture is verified in MATLAB and all processor modules and the switching unit implemented in Verilog HDL and Schematic Capture. A prototype simulator is integrated and synthesized for Xilinx V5-330t-1 as the target FPGA. While not dependent on particular IP (Intellectual Property) cores, the whole implementation is based on Xilinx IP cores including IEEE-754 64-bit floating-point adder and multiplier cores. The synthesize results and performance analyses are provided.