The thesis uses an up-down conversion architecture to realize a wideband frequency synthesizer for digital video broadcasting (DVB) transmission system. At first, the theoretical analysis of this architecture is performed to understand the mechanism to suppress the phase noise in an optimal way. Then, the simulations using Matlab and ADS are carried out to predict the phase noise performance. Based on the above efforts, a 50 MHz ~ 1 GHz wideband frequency synthesizer hybrid circuit is implemented and its phase noise performance, corresponding to different choices of the reference sources, is finally discussed. The second part of this thesis is to extend the up-down conversion architecture to an offset phase-locked loop (PLL) architecture for wideband frequency synthesizers. The difference from the conventional offset PLLs is the phase locking of the signal at either the sum or the difference frequency of two voltage-controlled oscillators (VCOs) to the reference source for the purpose of wideband operation. The phase noise analysis of the proposed offset PLL architecture is provided. In the experiments, a 300 MHz ~ 3.6 GHz wideband frequency synthesizer hybrid circuit is implemented to verify the analyzed phase noise results. In addition, a CMOS wideband frequency synthesizer chip using the proposed offset PLL architecture has been realized. Moreover, another two CMOS wideband frequency synthesizer chips are included in this thesis. It is worth mentioning that the VCOs in these two frequency synthesizer chips use the switched capacitor and inductor techniques to achieve a wideband operation.

This thesis presents a wide tuning, low phase noise CMOS integer-N frequency synthesizer with 1.8V power supply. The frequency synthesizer is designed using the TSMC 0.18£gm CMOS 1P6M technology. The proposed frequency synthesizer consists of a phase-frequency detector, a charge pump, a low-pass loop filter, a voltage control oscillator, an auto-band selection (ABS), an optimum-band selection (OBS), and a pulse-swallow divider. In system design, we present the new architecture for voltage-controlled oscillator with switched capacitors technique with a lowered VCO gain (KVCO) to achieve wide tuning range and low phase noise in order to cover the desired operating frequency bands and to accommodate process, voltage, and temperature (PVT) variations. The ABS accomplishes the efficient search for a VCO discrete tuning curve among a group of frequency sub-bands. It is apparent to reduce the calibration time by adopting the binary search algorithm to select the calibration word. However, the variation of Kvco across different channels can still be large after the execution of ABS. There might be many sub-bands covering the desired frequency. Hence the sub-band which is selected by ABS could not be an optimum choice for the minimum Kvco variation. The OBS is proposed to implement an algorithm in order to find the optimum solution which has the minimum Kvco variation and covers the desired frequency. The Kvco variation is quantified by OBS and using this value to adjust the charge pump current. Therefore, Loop bandwidth and stability were maintained across the operating range by using optimum-band selection(OBS) and a programmable charge pump.

In this thesis, a linear interpolation direct digital frequency synthesizer (DDFS) with improved structure to simplify the hardware complexity by correction block is proposed. Correction block is mainly used to compensate for the error curve of linear interpolation DDFS. From the analysis of these error curves, these error curves have similar behavior between each others. After selecting an error curve, the other error curves can be derived and multiplied by a fixed scale. From the simulation results, the correction block using the above method can improve about 12 dB spurious frequency dynamic range (SFDR). The goal of the DDFS designed in this thesis is to achieve 80 dB SFDR. Minimum required number of bits for each block in the proposed DDFS is carefully selected by simulation. In general, DDFS with piecewise linear interpolation theoretically needs 32 segments of piecewise linear interpolation to achieve 84 dB SFDR. In this thesis, 16 segments of piecewise linear interpolation with correction block can achieve the target SFDR. The chip¡¦s simulation is implemented by TSMC standard 0.13um 1P8M CMOS process with core area 78.11 x 77.49 um2.

The cost to test chips has risen tremendously. Additionally, the process for testing all functionalities of both analog and digital part is far from simple. One attractive option is moving some or all of the testing functions onto the chip itself leading to the use of built-in self-tests (BISTs). The frequency generator or frequency synthesizer is a key element of the BIST. It generates the clock frequencies needed for testing. A wide-band frequency synthesizer is designed in the project. The architecture of a PLL is analyzed as well as the modifications carried out. The modified structure has three blocks: basic PLL based frequency synthesizer, frequency down-converter, and output selector. Each of these blocks is analyzed and designed. This frequency synthesizer system overcomes challenges faced by the traditional PLL based frequency synthesizer.

The frequency synthesizer, which performs the main role of carrier generation for the down-conversion/up-conversion operations, is a key building block in radio transceiver front-ends. The design of a synthesizer for a 2.4 GHz IEEE 802.15.4/Zigbee transceiver forms the core of this work. This thesis provides a step-by-step procedure for the design of a frequency synthesizer in a transceiver environment, from the mapping of standard-specifications to its integrated circuit implementation in a CMOS technology. The results show that careful system level planning leads to high-performance realizations of the synthesizer. A strategy of using different supply voltages to enhance the performance of each building block is discussed. A section is presented on layout and board level issues, especially for radio-frequency systems, and their effect on synthesizer performance. The synthesizer consumes 15.5 mW and meets the specifications of the 2.4 GHz IEEE 802.15.4/Zigbee standard. It is capable of 5 GHz operation with a VCO sensitivity of 135 MHz/V and a tuning range of 700 MHz. It can be seen that the adopted methodology can be used for the design of high-performance frequency synthesizers for any narrow-band wireless standard.

This thesis includes two topics. The first topic is an ADFS¡]All Digital Frequency Synthesizer¡^using a Flying Adder architecture. The second one is a low-power and low-latency 2-dimensional bypassing signed multiplier. In the first topic, the ADFS is implemented by only using the standard cell library of TSMC¡]Taiwan Semiconductor Manufacturing Company¡^0.18 £gm 1P6M CMOS process. The turn-around time is effectively reduced. Furthermore, the portability and reusability of the proposed design is significantly enhanced. The design provides stable clock signals with fast switching time. In the second topic, the proposed multiplier is carried out by Baugh-Wooley algorithm using 2-dimensional bypassing units. The proposed bypassing units automatically skip redundant signal transitions when either the horizontally¡]row¡^partial products or vertically¡]column¡^operands are zero.

This thesis is composed of three parts. In the first part, analysis and discussion of phase noise in phase-locked loop is made. Because OFDM upconverter requires high phase noise performance, we therefore study the mechanism of noise suppression in a proposed dual phase-locked loop, and then derive the formula to predict the circuit characteristics. In the second part, experiment and simulation of a dual phase-locked loop is performed for comparison. The experiment uses hybrid circuit combined with related equipment and components to measure the noise suppression characteristics in a dual phase-locked loop. The simulation relies on the component behavioral model in ADS. Comparison between simulation and measurement shows good agreement. In the third part, this thesis carries out a 1.55¡V2.3 GHz frequency synthesizer RFIC design for DVB up-down architecture using TSMC 0.18£gm CMOS process. The test results validate the chip design.

The rapid growth of the market for short-range wireless devices, with standards such as Bluetooth and Wireless LAN (IEEE 802.11) being the most important, has created a need for highly integrated transceivers that target drastic power and area reduction while providing a high level of integration. The radio section of the devices designed to establish communications using these standards is the limiting factor for the power reduction efforts. A key building block in a transceiver is the frequency synthesizer, since it operates at the highest frequency of the system and consumes a very large portion of the total power in the radio. This dissertation presents the basic theory and a design methodology of frequency synthesizers targeted for short-range wireless applications. Three different examples of synthesizers are presented. First a frequency synthesizer integrated in a Bluetooth receiver fabricated in 0.35μm CMOS technology. The receiver uses a low-IF architecture to downconvert the incoming Bluetooth signal to 2MHz. The second synthesizer is integrated within a dual-mode receiver capable of processing signals of the Bluetooth and Wireless LAN (IEEE 802.11b) standards. It is implemented in BiCMOS technology and operates the voltage controlled oscillator at twice the required frequency to generate quadrature signals through a divide-by-two circuit. A phase switching prescaler is featured in the synthesizer. A large capacitance is integrated on-chip using a capacitance multiplier circuit that provides a drastic area reduction while adding a negligible phase noise contribution. The third synthesizer is an extension of the second example. The operation range of the VCO is extended to cover a frequency band from 4.8GHz to 5.85GHz. By doing this, the synthesizer is capable of generating LO signals for Bluetooth and IEEE 802.11a, b and g standards. The quadrature output of the 5 - 6 GHz signal is generated through a first order RC - CR network with an automatic calibration loop. The loop uses a high frequency phase detector to measure the deviation from the 90° separation between the I and Q branches and implements an algorithm to minimize the phase errors between the I and Q branches and their differential counterparts.

No description available.

Sintetizadores de Freqüências são circuitos que geram sinais em freqüências pré-determinadas, sendo estes sinais usados tanto na recepção como na transmissão de Rádio Freqüência. Os circuitos Sintetizadores possuem diversos blocos, dentre os quais podemos citar, osciladores controlados por tensão (VCO Voltage-Controlled Oscillator), divisores programáveis (Prescaler), comparadores de fase (DFF Detectores de Fase e Freqüência), bombas de carga (CP Charge Pump) e Filtros Passa Baixas (LPF Low Pass Filters). Em 2003 foi projetado por Angel M.G. Argüello [Ar04] um circuito Sintetizador de Freqüências com arquitetura tipo Integer-N. Este circuito, projetado para ter banda centrada em torno de 2,4 GHz e 16 canais de 4,78 MHz, foi implementado na tecnologia CMOS 0,35 µm da AMS (Austrian Micro Systems), que possui quatro níveis de metais e dois níveis de polisilício. Após testes do circuito as seguintes conclusões sobre seu funcionamento foram derivadas: o circuito funcionou qualitativamente como projetado, sintetizando 16 tons de freqüência; o ruído de fase medido ficou acima do valor desejado; a potência consumida esteve dentro dos valores previstos, porém elevada. No decorrer de 2004 foram feitas alterações no layout do circuito de Argüello com o objetivo de melhorar o ruído de fase. Estas alterações serviram como estudo preliminar para este trabalho. Dando continuidade ao desenvolvimento de Sintetizadores, em 2005 foram estudadas novas estruturas e layouts mais eficientes no tocante a ruído de fase, dando-se especial atenção às alimentações dos circuitos digitais e analógicos e ao isolamento entre os mesmos. Um novo circuito Sintetizador foi desenvolvido para aplicações em sistemas ZigBee, que operam na banda de freqüência entre 2,400 GHz a 2,485 GHz, com 16 canais de largura igual 2 à 5 MHz. Resultados de simulação sobre o circuito projetado apontaram o funcionamento adequado, com consumo de potência inferior a 32 mW para tensão de alimentação de 3,3 V. / Frequency Synthesizers are circuits that generate pre-determined frequencies, used in both radio frequency reception and transmission. The Synthesizer circuits are composed by several blocks, such as Voltage-Controlled Oscillator (VCO), Prescaler, PFD (Phase/Frequency Detector), Charge Pump (CP), and Low Pass Filters (LPF). In 2003, an Integer-N architecture Frequency Synthesizer circuit was developed by Angel M.G. Argüello [Ar04]. This circuit, designed to have a band centered around 2.4 GHz and 16 channels with a 4.78 MHz, were implemented with the 0.35 µm CMOS technology from AMS (Austrian Micro Systems), using four metal levels and two polisilicon levels. After the circuit tests, the following conclusions about its operation were derived: the designed circuit operated as expected, generating 16 tons of frequency; the phase noise stayed above of the desired value; the power consumption were within the expected values although high. During the year of 2004, several modifications in the Argüello circuit layout have been done in order to improve the phase noise. These modifications were a preliminary study to this work. Advancing in the development of Synthesizers, in 2005 new structures and more efficient layouts, in terms of noise, were studied, with special attention given to the digital and analog power supplies and their isolation. A new Synthesizer was developed for applications with the ZigBee, which operates with frequencies from 2.400 GHz to 2.485 GHz and 16 channels of 5 MHz. The simulation results pointed out the correct operation of the circuit, with power consumption lower than 32 mW for power supply of 3.3 V.