A pulse-laser based time-resolved photocurrent (TRPC) and photoluminescence (TRPL) system with a programmable Boxcar integrator/averager system incorporated was implemented to investigate the optical properties and charge carrier dynamics in a GaInP/GaAs single-junction photovoltaic device for the purposes of understanding fundamental optoelectronic processes in the solar cell. The implementation of whole system was realized by integrating the instrument of a Boxcar averager system with a pulse laser source + spectroscopic facilities. The delay time control and data acquisition were organized by the software code. The effects of the hardware configurations and the software parameters on the performance of the system were particularly addressed for the optimization of measurement conditions and precisions. Two main functions of TRPC and TRPL with a wide time range were demonstrated for the system. The system was employed to measure temperature- and bias voltages-dependent TRPC and TRPL spectra of a GaInP/GaAs single-junction photovoltaic device. The spectral data show a lot of information about the transient dynamic behaviors of photogenerated charge carriers in the device, including both the rise and decay processes. Interestingly, the measured time-resolved photocurrent curves are characterized by a fast rising edge followed by a relatively slow decay process as the temperature increases. Relevant theoretical calculations and analysis to the experimental curves were also carried out to understand diffusion and transport processes of charge carriers inside the device. The results show that the variation in temperature and reverse biases results in the structural change in the space charge region of the P-N junction and therefore affects the rise and decay time constants of the time-resolved photocurrent. The TRPL spectral data give information of mid-way radiative recombination of charge carriers in the device. / published_or_final_version / Physics / Master / Master of Philosophy

Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2004. / Includes bibliographical references (leaves 74-82). Also available in electronic version. Access restricted to campus users.

Thesis (M.E.E.)--University of Delaware, 2005. / Principal faculty adviser: Keith Goossen, Dept. of Electrical & Computer Engineering. Includes bibliographical references.

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Presented thesis is focused on the study of properties of Ga and GaN nanostructures on graphene. In the theoretical part of the thesis a problematics of graphene and GaN fabrication is discussed with a focus on the relation of Ga and GaN to graphene. The experimental part of the thesis deals with the depositions of Ga on transferred CVD-graphene on SiO2. The samples are analyzed by various methods (XPS, AFM, SEM, Raman spectroscopy, EDX). The properties of Ga on graphene are discussed with a focus on the surface enhanced Raman scattering effect. Furthermore, a deposition of Ga on exfoliated graphene and on graphene on a copper foil is described. GaN is fabricated by nitridation of the Ga structures on graphene. This process is illustrated by the XPS measurements of a distinct Ga peak and the graphene valence band during the process of nitridation.

The main objective of this study was to determine fundamental information related to ionbeam-induced damage to gallium arsenide (GaAs). The study covers experimental results concerning defect creation in GaAs versus parameters such as implantation energy, nature of GaAs substrate, crystalline orientation, and annealing. Transport and deep level transient spectroscopy (DLTS) results are presented for 50 keV Si-implanted and RTA (rapid thermal annealing) GaAs with (100) and (211) substrate orientations. Several electron traps are identified and their possible origins discussed. It is observed that (211) GaAs, after Si-implantation and RTA, has higher residual damage than (100) oriented GaAs. The electrical properties of active GaAs on Cr-doped and undoped GaAs substrates are compared. The DLTS response of active layers on Cr-doped GaAs is significantly different from those on undoped GaAs. A viable explanation that accounts for this difference is presented. The effects of furnace annealing on electrical properties of 50 keV, 4 x 10¹³ cm⁻² Si-implanted GaAs are addressed. A correlation between the structural recovery and electrical activation is established. The effects of 2 and 6 MeV Si implantation followed by RTA on the electrical characteristics of GaAs are investigated in detail. MeV Si-implantation and RTA generates active buried layers in GaAs. The buried layer quality is found to be at least comparable to a similarly processed keV Si-implanted active GaAs layer. The deep traps in MeV-implanted GaAs are identified and explained in terms of their probable origins. The deep level behavior of MeV Si-implanted and RTA GaAs is distinctly different from keV Si-implanted and RTA GaAs. This difference is largely due to the dynamic annealing occurring during MeV implantation. MESFETs formed on MBE-grown Al_.35Ga_.65As and low temperature MBE-grown GaAs buffer layers have shown peculiar characteristics (improved transconductance, sharper carrier profile, variability in threshold voltage, significant backgating, etc.). The effects of Al_.35Ga_.65As buffers and low temperature GaAs buffers on the electrical properties of the overlying active GaAs are investigated. Transport, DLTS, and SIMS (Secondary Ion Mass Spectroscopy) measurements are employed to explain the abnormalities in buffered MESFETs. Deep states and impurities are identified in buffers; they appear to migrate toward the channel-buffer interface during processing. The defects originating from the buffer are correlated to the performance of MESFETs formed on them. The effects of ion processing parameters, substrate chemistry, buffer layers, and annealing on the electrical characteristics of active GaAs layers are identified. An understanding of these effects is extremely critical to obtain reproducible devices with desirable characteristics. / Ph. D.

La vie dans la société contemporaine a changé énormément depuis l’invention du premier transistor électronique en 1947. L’apparition des transistors a permis la miniaturisation de systèmes électroniques de toute sorte dont la performance des transistors est aussi un aspect essentiel. Présentement, dans les marchés de semi-conducteurs à forte puissance et dans le secteur des technologies de l’information et des communications (TIC), les transistors GaN (Eg = 3,42 eV) présentent des avantages par rapport à leurs concurrents en Si et en GaAs pour les applications d’amplificateurs de puissance RF, la rectification et la commutation à forte puissance. La densité de puissance atteinte par les transistors GaN à effet de champ à haute mobilité (GaN-HEMTs) a dépassé 40 W∙mm[indice supérieur -1] à 4 GHz [Wu, Y.F. et al 2006]. Cependant, la génération de chaleur dans le canal provoque une augmentation de la température du semi-conducteur (autoéchauffement) qui provoque à la fois une diminution de la mobilité des électrons, ce qui va diminuer la performance du dispositif. Si la température du dispositif dépasse certaines limites, le dispositif risque de se dégrader de façon permanente avec un impact négatif sur la fiabilité [Nuttinck, S. et al., 2003]. Ainsi, il est très important de déterminer de façon fiable la température du canal dans les conditions réelles de fonctionnement pour modéliser le comportement des composants et pour obtenir les niveaux de performance et de fiabilité requises pour le progrès de cette technologie prometteuse. Ce projet vise au développement d’une nouvelle méthode de mesure de la température du canal des HEMTs AlGaN/GaN par contact direct avec les dispositifs, qui soit pratique et ne demande pas des systèmes sophistiqués ni dispendieux. Ainsi, on a réalisé la conception, la fabrication et la caractérisation d’une µRTD prototype potentiellement intégrable dans les dispositifs HEMT GaN. On a obtenu des capteurs qui fonctionnent de façon quasi linéaire dans une portée de températures de 25 à 275 °C et potentiellement au-delà de ces limites. On a réalisé des échantillons de transistors GaN avec des µRTDs intégrés, on a développé des dispositifs auxiliaires pour la calibration de µRTDs et pour la réalisation des mesures de température de canal (Tch) sous plusieurs conditions de polarisation. Dans un échantillon prototype, les valeurs de Tch mesurées avec le µRTD sont en accord avec des simulations 3D à éléments finis à plusieurs conditions de polarisation d’un dispositif sans-grille. Les mesures montrent des effets négligeables de perturbation électrique entre le dispositif et la µRTD [Arenas, O., et al., 2014 A]. Sur des échantillons de deuxième génération, on a mesuré la T[indice inférieur ch] d’HEMTs GaN sous plusieurs conditions de polarisation sur substrats en SiC et en saphir pour obtenir une carte Ids-Vds-Tch pour chaque dispositif [Arenas, O., et al., 2014 B]. Ainsi, les résultats obtenus démontrent que l’on peut mesurer la Tch d’un HEMT GaN polarisé en DC avec un µRTD avec peu d’interférence électrique et peu de perturbation thermique sans avoir besoin d’équipements sophistiqués ni onéreux. À l’avenir la méthode proposée peut potentiellement être appliquée sur dispositifs de plus petite taille si l’on utilise des technologies de fabrication basées sur la lithographie par faisceau d’électrons. Ainsi, elle pourra bientôt être disponible dans les plaques des dispositifs de production et de recherche.

published_or_final_version / abstract / Physics / Doctoral / Doctor of Philosophy

published_or_final_version / abstract / Physics / Doctoral / Doctor of Philosophy