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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
41

Voltage and temperature dependent gate capacitance and current model for high-K gate dielectric stack

Fan, Yang-yu. January 2002 (has links) (PDF)
Thesis (Ph. D.)--University of Texas at Austin, 2002. / Vita. Includes bibliographical references. Available also from UMI Company.
42

Gate dielectrics on strained SiGe

Ngai, Tat. January 2002 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 2002. / Vita. Includes bibliographical references. Available also from UMI Company.
43

Investigation of electrical characteristics of III-V MOS devices with silicon interface passivation layer

Zhu, Feng, 1978- 10 September 2012 (has links)
To overcome the issues of mobility degradation and charge trapping in silicon high-κ MOSFET, a stacked Y₂O₃(top)/HfO2(bottom) gate dielectric on silicon substrate has been developed. Compared to the HfO₂ reference, the new dielectric shows similar scalability, but superior channel mobility and device reliability. The mobility improvement can be attributed to reduced remote phonon scattering, which is associated with the smaller ionic polarization of Y₂O₃, and the suppressed coulomb scattering due to less electron trapping in the bulk of high-κ layer, and reduced metal impurities in the substrate. The passivation mechanisms for the silicon IPL passivation technique in GaAs/[alpha]-Si IPL/high-κ MOS system have been investigated. We demonstrate the [alpha]-Si IPL thickness dependence and substrate type dependence of interface state density (Dit) for GaAs MOS capacitors. The interface state density is strongly correlated to the thickness and quality of un-oxidized Si IPL and its interaction with the underlying substrate. The results can be explained by the models related to the quantum well narrowing or the reduced local trap density as the unoxidized Si IPL layer thickness decreases. By using optimal Si IPL thickness (~10 Å), GaAs MOS devices can achieve the same interface quality, as its silicon counterpart. Using Si IPL to unpin the surface Fermi level, the selfaligned depletion-mode and enhancement-mode GaAs n-MOSFETs are demonstrated. In addition, the charge trapping and wear-out characteristics of the GaAs/Si IPL/HfO2/TaN MOS devices are systematically investigated. High performance In0.53Ga0.47As nMOSFETs with Si IPL and HfO2 gate oxide have been demonstrated. We systematically investigate the impacts of 1) Source/Drain activation temperature, 2) post deposition annealing (PDA) temperature, 3) In[subscrip 0.53]Ga[subscript 0.47]As channel doping concentration, 4) channel thickness and 5) Si IPL thickness on the transistor performances. With the [mu]m, V[subscript d]=50 mV), drive current of 158 mA/mm (L[subscript g]=5 [mu]m, V[subscript gs]=V[subscript th]+2 V, V[subscript d]=2.5 V), and the peak effective channel mobility of 1034 cm2/V-s. InP nMOSFETs with Si IPL and HfO₂ have been demonstrated. The effects of Si IPL on the transistor performances and reliability characteristics are investigated. It is found that even through InP is a forgiving channel material with respect to surface Fermi level pinning, applying silicon IPL still improves the transistor performance and reliability. But the choice of Si IPL is critical for device design. Both in-sufficient passivation and excessive Si IPL should be avoided. optimal combination of these impacting factors, excellent device characteristics have been obtained, including the peak transconductance of 7.7 mS/mm (Lg=5 μm, Vd=50 mV), drive current of 158 mA/mm (Lg=5 [mu]m, Vgs=Vth+2 V, Vd=2.5 V), and the peak effective channel mobility of 1034 cm2/V-s. InP nMOSFETs with Si IPL and HfO₂ have been demonstrated. The effects of Si IPL on the transistor performances and reliability characteristics are investigated. It is found that even through InP is a forgiving channel material with respect to surface Fermi level pinning, applying silicon IPL still improves the transistor performance and reliability. But the choice of Si IPL is critical for device design. Both in-sufficient passivation and excessive Si IPL should be avoided. / text
44

Voltage and temperature dependent gate capacitance and current model for high-K gate dielectric stack

Fan, Yang-yu 28 August 2008 (has links)
Not available / text
45

Study of germanium MOSFETs with ultrathin high-k gate dielectrics

Chen, Jer-hueih 28 August 2008 (has links)
Not available / text
46

Germanium MOS devices integrating high-k dielectric and metal gate

Bai, Weiping 28 August 2008 (has links)
Not available / text
47

Gate dielectrics on strained SiGe

Ngai, Tat 10 June 2011 (has links)
Not available / text
48

Germanium MOS devices integrating high-k dielectric and metal gate

Bai, Weiping, 1972- 05 August 2011 (has links)
Not available / text
49

Untersuchungen zur Kostenoptimierung für Hardware-Emulatoren durch Anwendung von Methoden der partiellen Laufzeitrekonfiguration

Beckert, René January 2008 (has links)
Zugl.: Chemnitz, Techn. Univ., Diss., 2008
50

Investigation of electrical characteristics of III-V MOS devices with silicon interface passivation layer

Zhu, Feng, January 1900 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 2008. / Vita. Includes bibliographical references.

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