Not available / text

No description available.

No description available.

No description available.

No description available.

Field programmable gate arrays are a class of integrated circuit that enable logic functions and interconnects to be programmed in almost real time. They can implement fine grained parallel computing architectures and algorithms in hardware that were previously the domain of custom VLSI. Field programmable gate arrays have shown themselves useful at exploiting concurrency in a range of applications such as text searching, image processing and encryption. When coupled with a microprocessor, which is more suited to computation involving complex control flow and non time critical requirements, they form a potentially versatile platform commonly known as a Reconfigurable Computer. Reconfigurable computing applications have traditionally had the exclusive use of the field programmable gate array, primarily because the logic densities of the available devices have been relatively similar in size compared to the application. But with the modern FPGA expanding beyond 10 million system gates, and through the use of dynamic reconfiguration, it has become feasible for several applications to share a single high density device. / Thesis (PhD)--University of South Australia, 2005.

Field programmable gate arrays are a class of integrated circuit that enable logic functions and interconnects to be programmed in almost real time. They can implement fine grained parallel computing architectures and algorithms in hardware that were previously the domain of custom VLSI. Field programmable gate arrays have shown themselves useful at exploiting concurrency in a range of applications such as text searching, image processing and encryption. When coupled with a microprocessor, which is more suited to computation involving complex control flow and non time critical requirements, they form a potentially versatile platform commonly known as a Reconfigurable Computer. Reconfigurable computing applications have traditionally had the exclusive use of the field programmable gate array, primarily because the logic densities of the available devices have been relatively similar in size compared to the application. But with the modern FPGA expanding beyond 10 million system gates, and through the use of dynamic reconfiguration, it has become feasible for several applications to share a single high density device. However, developing applications that share a device is difficult as the current design flow assumes the exclusive use of the FPGA resources. As a consequence, the designer must ensure that resources have been allocated for all possible combinations of loaded applications at design time. If the sequence of application loading and unloading is not known in advance, all resource allocation cannot be performed at design time because the availability of resources changes dynamically. The use of a runtime resource allocation environment modelled on a classical software operating system would allow the full benefits of dynamic reconfiguration on high density FPGAs to be realised. In addition to runtime resource allocation, other services provided by an operating system such as abstraction of I/O and inter-application communication would provide additional benefits to the users of a reconfigurable computer. This could possibly reduce the difficulty of application development and deployment. In this thesis, an operating system for reconfigurable computing that supports dynamically arriving applications is presented. This is achieved by firstly developing the abstractions with which designers implement their applications and a set of algorithm requirements that specify the resource allocation and logic partitioning services. By combining these, an architecture of an operating system for reconfigurable computing can be specified. A prototype implementation on one platform with multiple applications is then presented which enables an exploration of how the resource allocation algorithms interact amongst themselves and with typical applications. Results obtained from the prototype include the measurement of the performance loss in applications, and the time overheads introduced due to the use of the operating system. Comparisons are made with programmable logic applications run with and without the operating system. The results show that the overheads are reasonable given the current state of the technology of FPGAs. Formulas for predicting the user response time and application throughput based on the fragmentation of an FPGA are then derived. Weaknesses are highlighted in the current design flows and the architecture of current FPGAs must be rectified if an operating system is to become main-stream. For the tool flows this includes the ability to pre-place and pre-route cores and perform high speed runtime routing. For the FPGAs these include an optimised network, a memory management core, and a separate layer to handle dynamic routing of the network. / thesis (PhD)--University of South Australia, 2005.

Mannheim, Univ., Diss., 2006.

Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.

Recently, the more widespread use of three-dimensional (3-D) imaging modalities, such as magnetic resonance imaging (MRI), computed tomography (CT), positron emission tomography (PET), and ultrasound (US) have generated a massive amount of volumetric data. These have provided an impetus to the development of other applications, in particular telemedicine and teleradiology. In these fields, medical image compression is important since both efficient storage and transmission of data through high-bandwidth digital communication lines are of crucial importance. Despite their advantages, most 3-D medical imaging algorithms are computationally intensive with matrix transformation as the most fundamental operation involved in the transform-based methods. Therefore, there is a real need for high-performance systems, whilst keeping architectures exible to allow for quick upgradeability with real-time applications. Moreover, in order to obtain efficient solutions for large medical volumes data, an efficient implementation of these operations is of significant importance. Reconfigurable hardware, in the form of field programmable gate arrays (FPGAs) has been proposed as viable system building block in the construction of high-performance systems at an economical price. Consequently, FPGAs seem an ideal candidate to harness and exploit their inherent advantages such as massive parallelism capabilities, multimillion gate counts, and special low-power packages. The key achievements of the work presented in this thesis are summarised as follows. Two architectures for 3-D Haar wavelet transform (HWT) have been proposed based on transpose-based computation and partial reconfiguration suitable for 3-D medical imaging applications. These applications require continuous hardware servicing, and as a result dynamic partial reconfiguration (DPR) has been introduced. Comparative study for both non-partial and partial reconfiguration implementation has shown that DPR offers many advantages and leads to a compelling solution for implementing computationally intensive applications such as 3-D medical image compression. Using DPR, several large systems are mapped to small hardware resources, and the area, power consumption as well as maximum frequency are optimised and improved. Moreover, an FPGA-based architecture of the finite Radon transform (FRAT)with three design strategies has been proposed: direct implementation of pseudo-code with a sequential or pipelined description, and block random access memory (BRAM)- based method. An analysis with various medical imaging modalities has been carried out. Results obtained for image de-noising implementation using FRAT exhibits promising results in reducing Gaussian white noise in medical images. In terms of hardware implementation, promising trade-offs on maximum frequency, throughput and area are also achieved. Furthermore, a novel hardware implementation of 3-D medical image compression system with context-based adaptive variable length coding (CAVLC) has been proposed. An evaluation of the 3-D integer transform (IT) and the discrete wavelet transform (DWT) with lifting scheme (LS) for transform blocks reveal that 3-D IT demonstrates better computational complexity than the 3-D DWT, whilst the 3-D DWT with LS exhibits a lossless compression that is significantly useful for medical image compression. Additionally, an architecture of CAVLC that is capable of compressing high-definition (HD) images in real-time without any buffer between the quantiser and the entropy coder is proposed. Through a judicious parallelisation, promising results have been obtained with limited resources. In summary, this research is tackling the issues of massive 3-D medical volumes data that requires compression as well as hardware implementation to accelerate the slowest operations in the system. Results obtained also reveal a significant achievement in terms of the architecture efficiency and applications performance.