Kyoto University (京都大学) / 0048 / 新制・課程博士 / 博士(情報学) / 甲第19137号 / 情博第583号 / 新制||情||102 / 32088 / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 小野寺 秀俊, 教授 髙木 直史, 教授 佐藤 高史 / 学位規則第4条第1項該当

京都大学 / 0048 / 新制・課程博士 / 博士(情報学) / 甲第19137号 / 情博第583号 / 新制||情||102(附属図書館) / 32088 / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 小野寺 秀俊, 教授 髙木 直史, 教授 佐藤 高史 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM

A safe electrical connection between the human body and the recording circuit is required for the acquisition of physiological signals such as the electrocardiogram (ECG), electroneurogram (ENG), or electromyogram (EMG). The recording chip is conventionally connected to the human body through a blocking capacitor. The capacitor avoids any DC current flowing from the recording system into the patient¡¦s body in the case of chip failure. However, the large capacitor area in an integrated chip and its effect on the signal transform function make the use of a coupling capacitor undesirable. In principle, a DC-coupled system can be used to overcome this limitation. The DC-coupled amplifier connects directly to the patient. However, a DC failure current caused, for example, by a gate-oxide short failure could harm the patient. To detect a dangerous condition, a safety monitoring system is proposed in this thesis. The safety monitoring system applies a test signal and physiological signals to the amplifier input. The disappearance of the test signal in the event of circuit failure is detected at the amplifier output. The recording system can then be switched into a safe state. The analysis of the monitoring system, its design procedure and simulation results are presented in this thesis. Moreover, the first measured results are reported for a system realized as an integrated circuit in TSMC 0.35 £gm 2P4M CMOS process technology.

Les composants semi-conducteurs de puissance sont aujourd'hui au c?ur des systèmes de conversion d'énergie et sont de plus en plus employés dans le domaine des transports, notamment dans des applications critiques induites par l'émergence des véhicules hybrides et d'avions plus électriques. Durant l'exploitation des systèmes de conversion d'énergie, des contraintes significatives sont imposées aux composants semi-conducteurs de puissance, dégradant ainsi leur fonctionnement. Dans une application critique, ces dégradations peuvent activer la défaillance d'un système électrique et ainsi avoir des conséquences graves d'un point de vue économique et de sécurité. Il existe alors une forte demande concernant une compréhension des modes de défaillances et des mécanismes de vieillissement des composants semi-conducteurs de puissance. Il en est de même pour le développement de nouvelles techniques de caractérisations pour le suivi de leur vieillissement. Le suivi de l'évolution de paramètres de l'oxyde de grille de véhicules tests par le biais de la méthode Capacité-Tension ou C(V) - couramment employée en micro-électronique - et de la méthode de l'onde thermique ou MOT - développée au sein du Groupe Énergie et Matériaux de l'IES -, ainsi que leur adaptation à des composants semi-conducteurs de puissance, constituent l'essentiel du travail de cette thèse. Le couplage de la MOT à la C(V) a permis de localiser sommairement les charges injectées dans l'oxyde de grille des véhicules tests lorsqu'ils ont été soumis à des contraintes électriques similaires à celles subies dans les systèmes de conversion d'énergie. / Power semi-conductor devices are increasingly used as key parts of embedded power conversion systems in critical applications such as aerospace industry and ground transport. In such critical applications, these devices are submitted to harsh electrical, thermal and mechanical environments stresses which may significantly alter their reliability. An embedded power conversion system failure due to a power semi-conductor device breakdown may induce catastrophic results in terms of human safety, as well as economical dimensions. There is, indeed, a continuous demand on an increasing knowledge concerning the failure modes and the ageing mechanisms of power semi-conductor devices, as well as for development of new characterization techniques for ageing monitoring. The greatest part of the present work is focused on the monitoring of gate oxide properties evolutions of samples structures using the Capacitance-Voltage method (C-V method) -mainly employed in microelectronics- and the Thermal Step Method (TSM) -developed in Energy and Materials Group of IES-, as well as applying them to power semi-conductor devices. Coupling TSM and C-V method has allowed to approximately locate injected charges in the gate oxide of sample devices when submitted to electrical stresses comparable to the ones submitted to power semi-conductor devices.

No description available.

Compact Models are the physically based accurate mathematical description of the cir-cuit elements, which are computationally efficient enough to be incorporated in circuit simulators so that the outcome becomes useful for the circuit designers. As the multi-gate MOSFETs have appeared as replacements for bulk-MOSFETs in sub-32nm technology nodes, efficient compact models for these new transistors are required for their successful utilization in integrated circuits. Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide thickness. In this work we explore the possibility of developing models without this approximation, while preserving the computational efficiency at the same level. Such effort aims to generalize the compact model and also to capture the oxide thickness asymmetry effect, which might prevail in practical devices due to process uncertainties and thus affects the device performance significantly. However solution to this modeling problem is nontrivial due to the bias-dependent asym-metric nature of the electrostatic. Using the single implicit equation based Poisson so-lution and the unique quasi-linear relationship between the surface potentials, previous researchers of our laboratory have reported the core model for such asymmetric CDG MOSFET. In this work effort has been put to include Non-Quasistatic (NQS) effects, different small-geometry effects, and noise model to this core, so that the model becomes suitable for practical applications. It is demonstrated that the quasi-linear relationship between the surface potentials remains preserved under NQS condition, in the presence of all small geometry effects. This property of the device along with some other new techniques are used to develop the model while keeping the mathematical complexity at the same level of the models reported for the symmetric devices. Proposed model is verified against TCAD simulation for various device geometries and successfully imple-mented in professional circuit simulator. The model passes the source/drain symmetry test and good convergence is observed during standard circuit simulations.

L'étude de la fiabilité représente un enjeu majeur de la qualification des technologies de l'industrie de la microélectronique. Elle est traditionnellement étudiée en suivant la dégradation des paramètres des transistors au cours du temps, qui sert ensuite à construire des modèles physiques expliquant le vieillissement des transistors. Nous avons fait le choix dans ces travaux d'étudier la fiabilité des transistors à l'échelle microscopique, en nous intéressant aux mécanismes de ruptures de liaisons atomiques à l'origine de la création des défauts de l'oxyde de grille. Nous avons tout d'abord identifié la nature des défauts et modéliser leurs dynamiques de capture de charges afin de pouvoir reproduire leur impact sur des mesures électriques complexes. Cela nous a permis de développer une nouvelle méthodologie de localisation des défauts, le long de l'interface Si-SiO2, ainsi que dans le volume de l'oxyde. La mesure des dynamiques de créations de défauts pour des stress de type porteurs chauds et menant au claquage de l'oxyde de grille nous a permis de développer des modèles de dégradation de l'oxyde, prédisant les profils de défauts créés à l'interface et dans le volume de l'oxyde. Nous avons enfin établi un lien précis entre l'impact de la dégradation d'un transistor sur la perte de fonctionnalité d'un circuit représentatif du fonctionnement d'un produit digital.L'étude et la modélisation de la fiabilité à l'échelle microscopique permet d'avoir des modèles plus physiques, offrant ainsi une plus grande confiance dans les extrapolations de durées de vie des transistors et des produits. / Reliability study is a milestone of microelectronic industry technology qualification. It is usually studied by following the degradation of transistors parameters with time, used to build physical models explaining transistors aging. We decided in this work to study transistors reliability at a microscopic scale, by focusing on atomic-bond-breaking mechanisms, responsible of defects creation into the gate-oxide. First, we identified defects nature and modeled their charge capture dynamics in order to reproduce their impact on complex electrical measurements degradation. This has allowed us developing a new methodology of defects localization, along the Si/SiO2 interface, and in the volume of the gate-oxide. Defects creation dynamics measurement, for Hot Carrier stress and stress conditions leading to the gate-oxide breakdown, has allowed us developing gate-oxide degradation models, predicting generated defect profiles at the interface and into the volume of the gate-oxide. Finally, we established an accurate link between a transistor degradation impact on circuit functionality loss.Reliability study and modeling at a microscopic scale allows having more physical models, granting a better confidence in transistors and products lifetime extrapolation.

Depuis ses débuts, l’industrie de la microélectronique s’est fixé comme objectif d’augmenter les performances et la densité des circuits, en suivant la loi de Moore. Ainsi, depuis la commercialisation du premier circuit en 1971, les industriels se sont atteler à miniaturiser les transistors, ce qui améliore automatiquement leurs performances. Cela dit, à partir du nœud 28nm, l’électrostatique est devenue très difficile à contrôler, et de nouvelles architectures de transistor, tel que le FDSOI est proposée par STMicroelectronics pour remédier à cette problématique. Les dégradations par effets d’antenne, qui apparaissent lors des procédés plasma, provoque la dégradation de l’oxyde de grille des composants, et peuvent ainsi induire la perte des avantages offerts par cette nouvelle technologie. Dans ce contexte, l’évaluation de l’impact de ce phénomène sur le comportement électrique des transistors en technologie FDSOI est clé. Cela représente l’objectif principal de cette thèse. Tout d’abord, un protocole expérimental a été défini, basé sur des techniques de caractérisation des procédés plasma (structures d’antenne), et sur la caractérisation de la dégradation de l’oxyde de grille. Ensuite, un nouveau mode d’écoulement des charges durant les étapes plasma, spécifique à cette nouvelle technologie est proposé. Le comportement des principaux mécanismes de dégradation par effet d’antenne est aussi investigué. Le premier, est lié à la nonuniformité locale du plasma entre les nœuds du transistor, qui induit des dégradations de type porteurs chauds. Le second, est lié à la topographie des antennes, qui cause des effets d’ombrage électronique, et donc des déséquilibre en courant entre les nœuds du transistor. Enfin, un modèle basé sur un simulateur de circuit ELDO ®, et qui permet de reproduire le comportement de ce phénomène dans la technologie FDSOI est proposé. Ce dernier tient compte des caractéristiques des structures d’antenne ainsi que des paramètres plasma. Diverses solutions sont par la suite proposées pour réduire les tensions d’antenne, basées notamment sur des simulations modèles pour optimiser les paramètres des procédés plasma. Des solutions de prévention dès la conception des circuits sont aussi proposées. / Since its beginning, the microelectronic industry is aiming to increase the circuits performance and density, following Moore’s law. Hence, since the commercialization of the first circuit in 1971, the industry focuses on the transistor dimensions reduction, which improve the device performances. But, starting from the 28nm technological node, the electrostatic has become very difficult to control, and new device structure, such as the FDSOI, is proposed by STMicroelectronics to resolve this issue. The antenna effects, which occur during plasma processes, induce gate oxide damages, which can lead to the loss of those new technology benefits. In this context, the analysis of this phenomenon on the electrical behavior of FDSOI devices is key. This is the main objective of this work. First, an experimental protocol is defined, based on plasma processes characterization technique (antenna structures), and gate oxide damage characterization. Then, a charging flow mode specific to this new technology is proposed. The mechanisms linked to the antenna damages are also investigated. The first mechanism is linked to the plasma local nonuniformity between the device nodes, which induces a stress mode similar to hot carrier injection. The second mechanism is related to the antenna topography, which generates electron shading effect, thus promoting an electrical imbalance between the device nodes. Finally, a model based on the simulator circuit ELDO ®, which allows reproducing the behavior of this phenomenon on the FDSOI technology is proposed. This model takes into account the antenna structure characteristics and the plasma parameters. Based on the model simulations, various solutions to reduce the antenna voltages are proposed. Prevention rules during the circuit design were also proposed and implemented.

Neste trabalho, investigou-se capacitores MOS fabricados sobre superfícies irregulares contendo formas retangulares periódicas com 100 nm de altura, obtidas a partir de corrosão por plasma localizadas. Os óxidos de porta com 4,5 nm de espessura foram crescidos em ambientes ultrapuros de O2 ou pirogênico a fim de comparar a uniformidade de cobertura sobre os degraus verticais dos perfis retangulares. Foi mostrado que a oxidação pirogênica ou convencional na temperatura de 850 ºC permite obter óxidos de porta sobre degraus com altura de 100nm com baixa corrente de fuga e alto campo de ruptura. Esse comportamento pode ser interpretado como óxidos de porta perfeitamente amoldados sobre os degraus de 100nm de altura. O impacto deste resultado é agora a possibilidade de implementar óxidos de porta para transistores de porta envolvente e FinFETs. / In this work, it was investigated MOS capacitors fabricated onto periodic rectangular shapes, 100 nm in height, obtained by localized plasma etching onto silicon wafer surfaces. 4.5-nm gate oxide growth was performed in ultrapure dry O2 or pyrogenic environments in order to compare the coverage uniformity at the step edges of rectangular shapes defined onto the silicon surfaces. It was shown that pyrogenic and conventional oxidation at 850 ºC allows one to obtain gate oxides on 100nm-stepped silicon surfaces with low leakage current and high dielectric breakdown field. This behavior can be understood as highly conformal gate oxides over silicon steps with height of 100 nm. The impact of this result is now the feasibility of implementing gate oxides for surrounding gate transistors (SGT\'s) and FinFETs.

Neste trabalho, investigou-se capacitores MOS fabricados sobre superfícies irregulares contendo formas retangulares periódicas com 100 nm de altura, obtidas a partir de corrosão por plasma localizadas. Os óxidos de porta com 4,5 nm de espessura foram crescidos em ambientes ultrapuros de O2 ou pirogênico a fim de comparar a uniformidade de cobertura sobre os degraus verticais dos perfis retangulares. Foi mostrado que a oxidação pirogênica ou convencional na temperatura de 850 ºC permite obter óxidos de porta sobre degraus com altura de 100nm com baixa corrente de fuga e alto campo de ruptura. Esse comportamento pode ser interpretado como óxidos de porta perfeitamente amoldados sobre os degraus de 100nm de altura. O impacto deste resultado é agora a possibilidade de implementar óxidos de porta para transistores de porta envolvente e FinFETs. / In this work, it was investigated MOS capacitors fabricated onto periodic rectangular shapes, 100 nm in height, obtained by localized plasma etching onto silicon wafer surfaces. 4.5-nm gate oxide growth was performed in ultrapure dry O2 or pyrogenic environments in order to compare the coverage uniformity at the step edges of rectangular shapes defined onto the silicon surfaces. It was shown that pyrogenic and conventional oxidation at 850 ºC allows one to obtain gate oxides on 100nm-stepped silicon surfaces with low leakage current and high dielectric breakdown field. This behavior can be understood as highly conformal gate oxides over silicon steps with height of 100 nm. The impact of this result is now the feasibility of implementing gate oxides for surrounding gate transistors (SGT\'s) and FinFETs.