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The objective of the research presented in this thesis was to investigate the effects of wearout processes on the performance and reliability of CMOS bistable circuits. The main wearout process affecting reliability of submicron MOS devices was identified as hot-carrier stress (and the resulting degradation in circuit performance). The effect of hot-carrier degradation on the resolving time leading to metastability of the bistable circuits also have been investigated. Hot-carrier degradation was identified as a major reliability concern for CMOS bistable circuits designed using submicron technologies. The major hot-carrier effects are the impact ionisation of hot- carriers in the channel of a MOS device and the resulting substrate current and gate current generation. The substrate current has been used as the monitor for the hot-carrier stress and have developed a substrate current model based on existing models that have been extended to incorporate additional effects for submicron devices. The optimisation of the substrate current model led to the development of degradation and life-time models. These are presented in the thesis. A number of bistable circuits designed using 0.7 micron CMOS technology design rules were selected for the substrate current model analysis. The circuits were simulated using a set of optimised SPICE model parameters and the stress factors on each device was evaluated using the substrate current model implemented as a post processor to the SPICE simulation. Model parameters for each device in the bistable were degraded according to the stress experienced and simulated again to determine the degradation in characteristic timing parameters for a predetermined stress period. A comparative study of the effect of degradation on characteristic timing parameters for a number of latch circuits was carried out. The life-times of the bistables were determined using the life-time model. The bistable circuits were found to enter a metastable state under critical timing conditions. The effect of hot-carrier stress induced degradation on the metastable state operation of the bistables were analysed. Based on the analysis of the hot-carrier degradation effects on the latch circuits, techniques are suggested to reduce hot-carrier stress and to improve circuit life-time. Modifications for improving hot- carrier reliability were incorporated into all the bistable circuits which were re-simulated to determine the improvement in life-time and reliability of the circuits under hot-carrier stress. The improved circuits were degraded based on the new stress factors and the degradation effects on the critical timing parameters evaluated and these were compared with those before the modifications. The improvements in the life-time and the reliability of the selected bistable circuits were quantified. It has been demonstrated that the hot-carrier reliability for all the selected bistable circuits can be improved by design techniques to reduce the stress on identified critically stressed devices.

Semiconductor technology has already got into nanometer scale. As the dimension keeping scaling down, we can get more transistor in the same area, and furthermore the frequency and performance are also enhanced. But nowadays the development of the lithography technology has come to the neck; we must find another way to improve the performance of transistor. In this study, we fully discuss the electrical characteristics and the hot carrier effect as the channel of the N-MOSFETs being strained. In order to strain the channel, silicon substrate is bent by applying external mechanical stress, the lattice of channel will be strained after applying uniaxial tensile stress. Therefore, we successfully improve drain current and carrier mobility of NMOS, and the increasing rates are 22% and 30% respectively. In addition, we can understand the influence of hot carrier effect on strain silicon by bending silicon substrate with external mechanical stress. With the increase of curvature, substrate current goes up. We offer an explanation to verify this result.

Semiconductor technology has already got into nanometer scale. As the dimension keeping scaling down, we can get more transistor in the same area, and furthermore the frequency and performance are also enhanced. But nowadays the development of the lithography technology has come to the neck, we must find another way to improve the performance of transistor. The reliability is more important in the shorter and shorter device channel. In this study, we fully discuss the electrical characteristics of the hot carrier effect at various temperature of 65nm MOSFETs under external mechanical stress. In order to strain the channel, silicon substrate is bent by applying external mechanical stress, the lattice of channel will be strained after applying uniaxial tensile stress. Therefore, we successfully improve drain current and carrier mobility of NMOS, but the hot carrier effect is more serious. In addition, we can understand the influence of hot carrier effect on strain silicon by bending silicon substrate with external mechanical stress. With the increase of curvature, substrate current goes up. We offer an explanation to verify this result. The temperature effect is also measured. The drain current and mobility increased with the temperature decreasing, but the substrate current increased with temperature increasing.

The objective of this work is to develop an effective TCAD based hot-carrier degradation model in predicting the damage that a SiGe HBT undergoes as it is stressed across bias, time and temperature.

This thesis work is mainly focused on studying RF performance degradation of a low noise amplifier (LNA) circuit due to hot carrier effect (HCE) in both the weak and strong inversion regions. Since the figures of merit for the RF circuit characterization are gain, noise figure, input, and output matching, the LNA RF performance drift is evaluated in a Cadence SpectreRF simulator subject to these features. This thesis presents hot carrier induced degradation results of an LNA to show that the HCE phenomenon is one of the serious reliability issues in the aggressively scaled RF CMOS design, especially for long-term operation of these devices. The predicted degradation from simulation results can be used design reliable CMOS RF circuits.

In this thesis, the effect of the sample properties on the characteristics of the hot carrier luminescence in graphene is investigated. The present work focuses on the two main issues described below. The first issue is the modification effects of near-infrared pulsed laser excitation on graphene. For excitation fluences several orders of magnitude lower than the optical damage threshold, the interaction with ultrafast laser pulses is found to cause a stable change in the properties of graphene. This photomodification also results in a decrease of the hot photoluminescence intensity. The detailed analysis shows that ultrafast photoexcitation leads to an increase in the local level of hole doping, as well as a change in the mechanical strain. The variation of doping and strain are linked with the enhanced adsorption of atmospheric oxygen caused by the distortion of the graphene surface. These findings demonstrate that ultrashort pulsed excitation can be invasive even if a relatively low laser power is used. Secondly, the variation of the hot photoluminescence intensity with the increasing charge carrier density in graphene is investigated. The electro-optical measurements performed using graphene field-effect transistors show a strong dependence of the photoluminescence intensity on the intrinsic carrier concentration. The emission intensity has a maximum value in undoped graphene and decreases with the increasing doping level. The theoretical calculations performed using a refined two-temperature model suggest that the reduction of the photoluminescence intensity is caused by an increase in the hot carrier relaxation rate. The modification of the carrier relaxation dynamics caused by photoinduced doping is probed directly using the two-pulse correlation measurements. The discovered sensitivity of the hot photoluminescence to the intrinsic carrier concentration can be utilised for spatially-resolved measurements of the Fermi level position in graphene samples, offering an advantage in resolution and speed.

abstract: The scaling of transistors has numerous advantages such as increased memory density, less power consumption and better performance; but on the other hand, they also give rise to many reliability issues. One of the major reliability issue is the hot carrier injection and the effect it has on device degradation over time which causes serious circuit malfunctions. Hot carrier injection has been studied from early 1980's and a lot of research has been done on the various hot carrier injection mechanisms and how the devices get damaged due to this effect. However, most of the existing hot carrier degradation models do not consider the physics involved in the degradation process and they just calculate the change in threshold voltage for different stress voltages and time. Based on this, an analytical expression is formulated that predicts the device lifetime. This thesis starts by discussing various hot carrier injection mechanisms and the effects it has on the device. Studies have shown charges getting trapped in gate oxide and interface trap generation are two mechanisms for device degradation. How various device parameters get affected due to these traps is discussed here. The physics based models such as lucky hot electron model and substrate current model are presented and gives an idea how the gate current and substrate current can be related to hot carrier injection and density of traps created. Devices are stressed under various voltages and from the experimental data obtained, the density of trapped charges and interface traps are calculated using mid-gap technique. In this thesis, a simple analytical model based on substrate current is used to calculate the density of trapped charges in oxide and interface traps generated and it is a function of stress voltage and stress time. The model is verified against the data and the TCAD simulations. Finally, the analytical model is incorporated in a Verilog-A model and based on the surface potential method, the threshold voltage shift due to hot carrier stress is calculated. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2017

La cellule photovoltaïque à porteurs chauds se caractérise par une population électronique hors équilibre thermique avec le réseau, ce qui se traduit par une température électronique supérieure à la température du matériau. Il devient alors possible de récupérer non seulement l'énergie potentielle des porteurs, mais également leur énergie cinétique, et donc d'extraire un surcroît de puissance qui n'est pas exploitée dans des cellules conventionnelles. Cela permet d'atteindre des rendements potentiels proches de la limite thermodynamique. L'extraction des porteurs hors équilibre se fait au moyen de membranes sélectives en énergie afin de limiter les pertes thermiques. Dans cette thèse, l'influence de la sélectivité des contacts sur les performances de la cellule est analysée par des simulations de rendement. Il apparaît que ce paramètre est moins critique qu'annoncé dans la littérature, et que des rendements élevés sont possibles avec des contacts semi-sélectifs, permettant l'extraction de porteurs au dessus d'un seuil d'énergie. De tels contacts sont non seulement beaucoup plus facilement réalisables en pratique que des contacts sélectifs, mais sont également plus compatibles avec les densités de courant élevées qui sont attendues dans de tels dispositifs. Une méthodologie expérimentale est également proposée pour analyser la vitesse de thermalisation des porteurs hors équilibre. Des porteurs sont photogénérés par un laser continu et leur température en régime stationnaire est sondée par photoluminescence en fonction de la densité de puissance excitatrice. Un modèle empirique est obtenu reliant la puissance dissipée par thermalisation à la température électronique. Ce modèle est ensuite utilisé pour simuler le rendement de cellules présentant une thermalisation partielle des porteurs. Enfin, un rendement de cellule réaliste présentant une absorption non idéale, une vitesse de thermalisation mesurée sur des matériaux réels et des contacts semi-sélectifs est calculé. Il ressort qu'une augmentation substantielle de rendement est possible en comparaison d'une simple jonction ayant le même seuil d'absorption, mais que la vitesse de thermalisation observée est néanmoins trop élevée pour permettre de dépasser les records de rendement actuels. Des idées sont proposées afin d'améliorer les performances des structures étudiées. / A hot carrier solar cell is characterized by a carrier population in thermal non equilibrium with the lattice, that translates into carriers having a temperature higher than the material temperature. It then becomes possible to collect not only the carrier potential energy but also their kinetic energy, and thus to extract an additional power that is not used in conventional solar cells. This enables to reach a potential efficiency close to the thermodynamical limit. The extraction of carriers is made through energy selective membranes in order to reduce the heat loss. In this thesis, the impact of contact selectivity on the cell behaviour is investigated by simulating its efficiency. It appears that this parameter is not as crucial as what was said in the literature, and that a high efficiency is indeed possible with semi-selective contacts allowing carrier extraction above an energy threshold. Such contacts would not only be much easier to fabricate in practice, but are also more compatible with the high current densities that are expected in such devices. An experimental method is also proposed to determine the non equilibrium carrier cooling rate. Carriers are photogenerated by a continuous wave laser and their temperature in steady state conditions is probed by photoluminescence as a function of the excitation power density. An empirical model is obtained that relates the power dissipation due to carrier thermalization to the electron temperature. Such model can then be used in a hot carrier solar cell model to take heat losses into account. Finally, the efficiency of a realistic cell having non ideal absorption, a cooling rate measured on real materials and semi-selective contacts is simulated. It turns out that a substantial efficiency enhancement is possible compared to single junction cells with the same band gap, but that the cooling rate measured on samples is nevertheless too high to exceed today's efficiency records. Ideas are proposed to improve the performance of the structure under investigation.

This thesis describes the development of experimental methods to probe the nanoscale light-matter interactions in photonic and plasmonic nanostructures. The first part of this thesis presents the experimental findings on the temperature evolution of optical properties in important plasmonic materials. Understanding the influence of temperature on the optical properties of thin metal films - the material platforms for plasmonics - is crucial for the design and development of practical devices for high temperature applications in a variety of research avenues, including plasmonics, novel energy conversion technologies and near-field radiative heat transfer. We will first introduce a custom built experimental platform comprising a heating stage integrated into a spectroscopic ellipsometer setup that enables the determination of optical properties in the wavelength range from 370 nm to 2000 nm at elevated temperatures, from room temperature to 900 ^oC. Subsequently, the temperature dependent complex dielectric functions of gold, silver and titanium nitride thin films that were obtained using the above described experimental platform will be presented. Furthermore, the underlying microscopic physical processes governing the temperature evolution and the role of film thickness and crystallinity will be discussed. Finally, using extensive numerical simulations we will demonstrate the importance of incorporating the temperature induced deviations into numerical models for accurate multiphysics modeling of practical high temperature nanophotonic applications.<div><br></div><div>The second part of this thesis focuses on the development of experimental techniques to quantify the nanoscale steady-state energy distributions of plasmonic hot-carriers. Such hot-carriers have drawn significant research interest in recent times due to their potential in a number of applications including catalysis and novel photodetection schemes circumventing bandgap. However, direct experimental quantification of steady-state energy distributions of hot-carriers in nanostructures, which is critical for systemic progress, has not been possible. Here, we show that transport measurements from suitably chosen single molecular junctions can enable the quantification of plasmonic hot-carrier distributions generated via plasmon decay. The key idea is to create single molecule junctions - using carefully chosen molecules featuring sharp molecular resonances - between a plasmonic nanostructure and the gold tip of a scanning tunneling microscope, and quantify the hot-carrier distributions form the current flowing through the molecular junctions with and without plasmonic excitation at various voltage biases. Using this approach, we reveal the fundamental role of surface-scattering assisted absorption - Landau damping - and the contributions of different plasmonic modes towards hot-carrier generation in tightly confined nanostructures. The approach pioneered in this work can potentially enable nanoscale experimental quantification of plasmonic hot-carriers in key nanophotonic and plasmonic systems.<br></div>