Diese Arbeit beschäftigt sich mit der „First-Principles“ atomskaligen Modellierung der HfO2-basierten high-k-Gate-Isolatorschichten der Metalloxid-Halbleiter-Feldeffekttransistoren. Die theoretischen Untersuchungen basieren auf Dichtefunktionaltheorie und Nichtgleichgewicht-Greensche-Funktion-Formalismen. Eine der wichtigsten Eigenschaften eines Gate-Isolators ist der Wert seiner Bandlücke. Die Bandlücke eines gemischten Festkörpers aus SiO2 und ZrO2 oder HfO2 wird auf der Grundlage der „Generalized Quasi-Chemical“ Approximation in Kombination mit dem „Cluster Expansion“ Ansatz berechnet. Zu diesem Zweck wurde Dichtefunktionaltheorie für die Berechnung der Eigenschaften verschiedener Konfigurationen möglicher Elementarzellen durchgeführt. Es wurde ein fast linearer Verlauf für die Bandlücke eines aus SiO2 und HfO2 gemischten Festkörpers berechnet. Im Vergleich zu dem üblichen SiO2 Gate-Isolator, haben die high-k-Gate-Isolatoren eine höhere Defektdichte, die hauptsächlich aus Sauerstoffleerstellen bestehen. Dies führt zu mehreren Problemen, wie zum Beispiel höherer Leckstrom, Schwellenspannungsverschiebung und Degradation des Gateoxids. Daher wurde eine umfassende Untersuchung der verschiedenen Eigenschaften von Sauerstofffehlstellen in HfO2 durchgeführt, indem wichtige Parameter wie zum Beispiel die Formationsenergien und die Lage der Defektniveaus in der Bandlücke berechnet wurden. Es wurde durch die theoretischen Berechnungen gezeigt, dass die schädlichen Auswirkungen von Sauerstofffehlstellen durch die Einführung von Lanthan-Atomen in dem HfO2 Kristallgitter teilweise zu verringern sind. Energetisch gesehen bevorzugen die Lanthan-Atome die Hf-Gitterplätze in der Nachbarschaft einer Sauerstofffehlstelle und führen dadurch zu der Passivierung durch Sauerstoffleerstelle induzierten Defektniveaus. Die high-k-Isolatorschicht in den heutigen Transistoren besteht aus drei Schichten: einem Metallgate, einer HfO2-Schicht als Haupt-Gate-Isolator und einer sehr dünnen SiO2 Übergangsschicht zwischen Gateoxid und Si. Die Einführung eines Metallgates führt zu einigen Problemen bei der Einstellung einer geeigneten Schwellenspannung in den Transistoren. Theoretische Berechnungen in einer komplexen Modellstruktur von der Si/SiO2/HfO2-Grenzfläche zeigen, dass die dotierten Lanthan-Atome energetisch die SiO2/HfO2-Grenzfläche bevorzugen, was wiederum ein Dipolmoment an der Grenzfläche erzeugt. Dieses Dipolmoment kann verwendet werden, um die richtige Schwellenspannung wieder einzustellen. Schließlich wird in den experimentellen Messungen festgestelltes progressives Degradationsverhalten von high-k-Gate-Isolatoren mit einem theoretischen Modell erklärt. Dieses Modell basiert auf ab-initio-Berechnungen und zeigt, wie die Erzeugung geladener Sauerstoffleerstellen und deren Migration unter der angelegten Gatespannung zu einer progressiven Erhöhung des Leckstroms und folglich zu einer Degradation der Isolatorschicht führt.:List of Figures 7 List of Tables 9 List of Symbols 10 List of Abbreviations 11 Chapter 1: Introduction 12 Chapter 2: Theory of Atomic-Scale First-Principles Calculations 15 2.1 Theoretical methods 15 2.2 Density functional theory 17 2.3 Non-equilibrium Green’s function formalism 23 Chapter 3: Calculations for Bulk High-k Materials 27 3.1 Bulk high-k materials 27 3.2 Crystalline insulators 27 3.3 Solid solutions 29 3.3.1 Cluster expansion approach 30 3.3.2 Band gap and bowing parameter 33 3.3.3 Calculation of internal stress 40 3.4 Leakage current 41 Chapter 4: Defects in Bulk High-k Materials 43 4.1 Defects in high-k gate dielectrics 43 4.2 Oxygen vacancies in monoclinic HfO2 44 4.2.1 Neutral oxygen vacancies 44 4.2.2 Charged oxygen vacancies 46 4.3 Hybrid functional 50 4.4 Double oxygen vacancies 56 4.5 Interaction of oxygen vacancies with La-doping 61 4.5.1 La doping in m-HfO2 61 4.5.2 Complex LaHfVO defects 64 Chapter 5: Interface Properties of High-k Gate Stack 72 5.1 high-k gate-stack 72 5.1.1 Atomic-scale model structure for a high-k gate-stack 72 5.1.2 Electronic structure 74 5.1.3 Leakage current 76 5.2 Band offset 80 5.3 Threshold voltage engineering with La doping 84 Chapter 6: Degradation of the High-k Gate Stack 90 6.1 Reliability issues in high-k gate-stack 90 6.2 Calculations and experimental methods 91 6.3 Leakage current 92 6.4 Defect generation 100 6.5 Explaining progressive SILC in high-k dielectrics 102 Chapter 7: Conclusions 104 Bibliography 106 Selbständigkeitserklärung 119 Danksagung 120 Lebenslauf 121 Veröffentlichungen 122 / This thesis deals with the first-principles atomic-scale modeling of the HfO2-based high-k gate-insulator layer of the metal-oxide-semiconductor field-effect transistors. The theoretical investigations are based on density functional theory and non-equilibrium Green's function formalisms. One of the important properties of the gate insulator is the value of its band gap. The band gap of amorphous solid mixtures of SiO2 and ZrO2 or HfO2 is calculated based on generalized quasi-chemical approximation combined with a cluster expansion approach, by performing density functional calculations on different configurations of possible unit cells. An almost linear variation of the band gap is obtained for solid mixtures of SiO2 and HfO2. One drawback of the high-k gate-insulator, comparing to the standard SiO2, is high density of defects, particularly oxygen vacancies, which leads to several problems such as enhancement of the leakage current, threshold voltage instability, and degradation of the gate-oxide. A comprehensive investigation of different properties of oxygen vacancies in HfO2 is conducted by the calculation of formation energies and induced trap levels. It is shown based on theoretical calculations that the harmful effects of oxygen vacancies can be partially healed by introducing lanthanum atoms into the defected HfO2 crystal. Lanthanum atoms energetically prefer to occupy Hf lattice sites close to the oxygen vacancies and passivate the induced defect levels. The state-of-the-art high-k gate-stacks consist of a metal-gate on a HfO2 layer, as the main part of the gate insulator, and a very thin SiO2 intermediate layer between high-k material and Si. The introduction of a metal-gate raises some problem in the adjustment of an appropriate threshold voltage. Theoretical calculations in a complex model structure of the Si/SiO2/HfO2 interface reveals that the lanthanum atoms energetically prefer to stay at the SiO2/HfO2 interface, which in turn results in a dipole moment. This dipole moment can be employed to adjust the threshold voltage in high-k/metal-gate stacks. Finally, a theoretical model, which can quiet well explain the experimental measurements, is introduced for the progressive degradation of the high-k gate-insulators. This model is based on ab-initio calculations and shows how the generation of charged vacancies and their migration under the applied gate voltage leads to the progressive enhancement of the leakage current and consequently to the degradation of the insulator layer.:List of Figures 7 List of Tables 9 List of Symbols 10 List of Abbreviations 11 Chapter 1: Introduction 12 Chapter 2: Theory of Atomic-Scale First-Principles Calculations 15 2.1 Theoretical methods 15 2.2 Density functional theory 17 2.3 Non-equilibrium Green’s function formalism 23 Chapter 3: Calculations for Bulk High-k Materials 27 3.1 Bulk high-k materials 27 3.2 Crystalline insulators 27 3.3 Solid solutions 29 3.3.1 Cluster expansion approach 30 3.3.2 Band gap and bowing parameter 33 3.3.3 Calculation of internal stress 40 3.4 Leakage current 41 Chapter 4: Defects in Bulk High-k Materials 43 4.1 Defects in high-k gate dielectrics 43 4.2 Oxygen vacancies in monoclinic HfO2 44 4.2.1 Neutral oxygen vacancies 44 4.2.2 Charged oxygen vacancies 46 4.3 Hybrid functional 50 4.4 Double oxygen vacancies 56 4.5 Interaction of oxygen vacancies with La-doping 61 4.5.1 La doping in m-HfO2 61 4.5.2 Complex LaHfVO defects 64 Chapter 5: Interface Properties of High-k Gate Stack 72 5.1 high-k gate-stack 72 5.1.1 Atomic-scale model structure for a high-k gate-stack 72 5.1.2 Electronic structure 74 5.1.3 Leakage current 76 5.2 Band offset 80 5.3 Threshold voltage engineering with La doping 84 Chapter 6: Degradation of the High-k Gate Stack 90 6.1 Reliability issues in high-k gate-stack 90 6.2 Calculations and experimental methods 91 6.3 Leakage current 92 6.4 Defect generation 100 6.5 Explaining progressive SILC in high-k dielectrics 102 Chapter 7: Conclusions 104 Bibliography 106 Selbständigkeitserklärung 119 Danksagung 120 Lebenslauf 121 Veröffentlichungen 122

La fiabilité des chaînes de conversion électrique dans les systèmes embarqués est un enjeu critique dans les applications où interviennent des contraintes liées à la sécurité des personnes ou à des aspects économiques non-négligeables. La maintenance préventive permet de surveiller le bon fonctionnement des maillons faibles de la chaîne de conversion, tels que les composants de puissance à semiconducteurs (IGBT à grille en tranchée) présents dans les convertisseurs d'électronique de puissance utilisés dans le domaine du transport. L'objectif de ce travail est d'évaluer la possibilité d'utiliser l'état de l'oxyde de grille comme indicateur de l'état opérationnel du composant, lorsque celui-ci est soumis à des contraintes thermo-électriques représentatives de son fonctionnement. Les résultats obtenus par couplage de différentes techniques non destructives (méthode capacité-tension et méthode de mesure des charges d'espace) mettent en évidence des évolutions de l'oxyde liées à des effets causés par les charges électriques dans les zones de la structure les plus contraintes.L'étude et la modélisation des phénomènes diélectriques dans les couches minces d'oxyde nécessitent de nouvelles méthodes de mesure de la charge électrique à haute résolution spatiale. Dans le présent travail, nous démontrons, à travers des simulations et des résultats expérimentaux, l'applicabilité d'une de ces techniques de caractérisation, « la méthode de l'impulsion thermique », sur ce type de structures de la microélectronique. Sa sensibilité aux fines zones de champ électrique localisées au niveau des interfaces est en particulier mise en évidence, en ouvrant des voies vers la mise au point de nouvelles techniques à haute résolution spatiale, basées sur des stimuli thermiques. / The reliability of the electrical conversion chains in embedded systems is a critical issue in applica-tions where the security of persons and the economic aspects are significant. Preventive maintenance allows monitoring the proper functioning of the « weak links » in the conversion chain, such as power semiconductors components (trench gate IGBT) present in the electronic power converters used in the transport sector. The aim of the present work is to evaluate the possibility of using the gate oxide state as an indicator of the operational state of the component when it is subjected to thermo-electrical stress such as during service. The results obtained by coupled non-destructive techniques (capacitance-voltage and space charges measurement methods) bring out changes in the oxide produced by electrical charges in the most stressed areas of the structure.The study and modeling of dielectric phenomena in thin oxide layers require new high resolution methods for measuring the electric charge. In this work, simulations and experimental results have been used to demonstrate the applicability of one of these techniques, « the Thermal Pulse Method », to this type of microelectronic structures. The electric field at interfaces detected due to the sensitivity of this method is highlighted, opening ways to the development of new techniques with high spatial reso-lution, based on thermal stimuli.

In this these, in order to enhance the n-channel organic field-effect transistor (OFET) performance, amino functionalized self-assembled monolayers (A-SAMs) which consist of amino groups, a well-known n-type dopant candidate, were introduced from the top of OFET surfaces and on the gate oxide surfaces. To obtain better understanding for optimization of OFET performances we attempted to elucidate the mechanism of surface doping and surface modification by A-SAMs. Both the surface doping and surface modification of the gate oxide approaches have individual pros and cons. One needs to take into account the surface energy properties of SAMs and the resulting OSC film structure and pick the most suitable method to introduce the SAM material to the OFET (either doping or oxide modification) in order to obtain optimized device performances. Our study strongly suggests that both surface doping and surface modification of the gate oxide with A-SAMs could enhance other semiconductor-based electronic device performances.:Abstract v Chapter 1. Introduction 1 Chapter 2. Theoretical Background 7 2.1. Organic Semiconductors (OSCs) 8 2.1.1. Semiconducting properties of organic molecules 8 2.1.2. Charge Transport Mechanism in OSCs 10 2.2. Organic Field-Effect Transistors (OFETs) 18 2.2.1. Operation Principle 18 2.2.2. Device Geometry of OFETs 20 2.2.3. Contacts (metal/semiconductor junction) in OFETs 21 2.2.4. Dielectric material for OFETs 23 2.2.5. Current-Voltage Characteristics of OFETs 25 2.3. Dominant contributors to OFET Performance 32 2.3.1. Molecular structure and Orientation of OSCs 32 2.3.2. Dielectric/OSC Interface 33 2.3.3. OSC/Contact Interface (Contact resistance) 35 2.3.4. Shallow and deep traps 36 2.4. Strategies to improve OFET performance 37 2.4.1. Introducing dopants to OFETs 37 2.4.2. Modification of Gate Oxide Layer with SAMs 44 Chapter 3. Experimental 51 3.1. Device Fabrication 52 3.1.1. Device type I - Substrate/ODTMS/PTCDI-C8/Au 53 3.1.2. Device type II - Substrate/ODTCS/N2200 (PNDI2OD-2T)/Au 53 3.1.3. Device type III - Substrate/SAMs/PTCDI-C8/Au 54 3.2. Surface doping process 56 3.2.1. Surface dopant – Aminosilanes (A-SAMs) 56 3.2.2. Surface doping method 56 3.3. Characterization 59 3.3.1. Material characterization 59 3.3.2. Surface-wetting characterization - Contact angle measurement 61 3.3.3. Micro-structure characterization - Atomic Force Microscopy (AFM) 62 3.3.4. Surface potential characterization – Kelvin Probe Force Microscopy (KPFM) 63 3.3.5. Molecular Structure Characterization - Grazing Incidence Wide Angle X-ray Scattering (GIWAXS) 64 3.3.6. Electrical Characterization - Current-voltage (I-V) measurement 66 Chapter 4. Result and Discussion 69 4.1. Optimization of OFETs based on PTCDI-C8 and N2200 70 4.1.1. PTCDI-C8 OFETs 70 4.1.2. N2200 OFETs 72 4.1.3. Device measurement condition 75 4.2. Investigation of Surface doping mechanism of Aminosilanes 77 4.2.1. Surface doping effect depending on the dopant processing method 77 4.2.2. Surface doping effect for different types of organic semiconductors 80 4.2.3. Surface doping effect for different types of surface dopants 89 4.2.4. Surface doping effect for different OSC grain sizes 92 4.2.5. Surface doping effect for different OSC film thicknesses 103 4.2.6. Molecular structure of the doped films identified by GIWAXS 106 4.2.7. Stability of the surface doped OFETs 107 4.2.8. Summary 111 4.3. Modification of the gate oxide with various self-assembled monolayers 112 4.3.1. The surface property of SAM-treated substrates 112 4.3.2. The relation between the OSC morphology and the field-effect mobility 115 4.3.3. The origin of the threshold voltage shift 126 4.3.4. Memristive effects in PTCDI-C8 devices on ODTMS 133 4.3.5. Summary 137 4.4. Comparison of the surface doping and the modification of the gate dielectric 138 4.4.1. The reliability factor of OFETs 138 4.4.2. The threshold voltages and field-effect mobility of OFETs 141 4.4.3. Density of Interfacial trap sites and SAM induced mobile carriers 143 4.4.4. Summary 144 Chapter 5. Conclusion 145 Bibliography 148 List of Figures 158 List of Tables 166 List of Equations 167 Acknowledgment 168 Erklärung zur Eröffnung des Promotionsverfahrens 169

The trend of electrification in transportation applications has led to the fast development of high-power-density power electronics converters. High-switching-frequency and high-temperature operations are the two key factors towards this target. Both requirements, however, are challenging the fundamental limit of silicon (Si) based devices. The emerging wide-bandgap, silicon carbide (SiC) power devices have become the promising solution to meet these requirements. With these advanced devices, the technology barrier has now moved to the compatible integration technology that can make the best of device capabilities in high-power-density converters. Many challenges are present, and some of the most important issues are explored in this dissertation. First of all, the high-temperature performances of the commercial SiC MOSFET are evaluated extensively up to 200 degree C. The static and switching characterizations show that the device has superior electrical performances under elevated temperatures. Meanwhile, the gate oxide stability of the device - a known issue to SiC MOSFETs in general - is also evaluated through both high-temperature gate biasing and gate switching tests. Device degradations are observed from these tests, and a design trade-off between the performance and reliability of the SiC MOSFET is concluded. To understand the interactions between devices and circuit parasitics, an experimental parametric study is performed to investigate the influences of stray inductances on the MOSFETs switching waveforms. A small-signal model is then developed to explain the parasitic ringing in the frequency domain. From this angle, the ringing mechanism can be understood more easily and deeply. With the use of this model, the effects of DC decoupling capacitors in suppressing the ringing can be further explained in a more straightforward way than the traditional time-domain analysis. A rule of thumb regarding the capacitance selection is also derived. A Power Electronics Building Block (PEBB) module is then developed with discrete SiC MOSFETs. Integrating the power stage together with the peripheral functions such as gate drive and protection, the PEBB concept allows the converter to be built quickly and reliably by simply connecting several PEBB modules. The high-speed gate drive and power stage layout designs are presented to enable fast and safe switching of the SiC MOSFET. Based on the PEBB platform, the state-of-the-art Si and SiC power MOSFETs are also compared in the device characteristics, temperature influences, and loss distributions in a high-frequency converter, so that special design considerations can be concluded for the SiC MOSFET. Towards high-temperature, high-frequency and high-power operations, integrated wire-bond phase-leg modules are also developed with SiC MOSFET bare dice. High-temperature packaging materials are carefully selected based on an extensive literature survey. The design considerations of improved substrate layout, laminated bus bars, and embedded decoupling capacitors are all discussed in detail, and are verified through a modeling and simulation approach in the design stage. The 200 degree C, 100 kHz continuous operation is demonstrated on the fabricated module. Through the comparison with a commercial SiC phase-leg module designed in the traditional way, it is also shown that the design considerations proposed in this work allow the SiC devices in the wire-bond structure to be switched twice as fast with only one-third of the parasitic ringing. To further push the performance of SiC power modules, a novel hybrid packaging technology is developed which combines the small parasitics and footprint of a planar module with the easy fabrication of a wire-bond module. The original concept is demonstrated on a high-temperature rectifier module with SiC JFET. A modified structure is then proposed to further improve design flexibility and simplify module fabrication. The SiC MOSFET phase-leg module built in this structure successfully reaches the switching speed limit of the device almost without any parasitic ringing. Finally, a new switching loop snubber circuit is proposed to damp the parasitic ringing through magnetic coupling without affecting either conduction or switching losses of the device. The concept is analyzed theoretically and verified experimentally. The initial integration of such a circuit into the power module is presented, and possible improvements are proposed. / Ph. D.

Dans le contexte écologique actuel, les équipementiers automobiles européens sont dans l’obligation de développer des systèmes innovants afin de réduire les rejets de gaz à effet de serre des véhicules. Les nouvelles applications électroniques micro-hybrides exigent le développement de stratégies quant à l’intégration des systèmes et la réduction des pertes. Ainsi, une proposition a consisté à réaliser des modules de puissance constitués de transistors MOSFETs basse tension fort courant. L’application de type alterno-démarreur plus communément nommée « Stop & Start »exige des composants toujours plus robustes et fiables du fait de la sollicitation en mode d’avalanche sous des températures pouvant atteindre 175°C.Les travaux de recherche présentés dans cette thèse portent donc sur l’aspect d’optimisation de la robustesse et de la fiabilité des composants. Tout d’abord, il était essentiel de comprendre l’avalanche et ses enjeux pour la technologie. Ensuite dans ce contexte, le procédé notamment autour de l’oxyde de grille a été amélioré afin de garantir la tenue en mode de sollicitation grille-source et grille-drain pour satisfaire les exigences de fiabilité. En outre, le développement d’un test innovant de la puce, dérivé du QBD, a permis d’évaluer précisément les modifications apportées sur le procédé de fabrication et d’être corrélé avec les résultats des essais de fiabilité. Enfin, le cycle de vie d’un MOSFET nécessite un suivi qualité précis qui se compose de deux aspects essentiels. En premier lieu, le suivi des paramètres électriques et de leur dérive par une analyse statistique « postprocessing». En second lieu, la mise en place d’un outil de traçabilité du module à la puce pour traquer les éventuels rejets dans l’application finale et remonter à la cause d’origine. Toutes les innovations présentées, dans ce mémoire, s’inscrivent dans une démarche novatrice de l’amélioration continue de la qualité des composants de type MOSFET de puissance / In the current ecologic context, the European automotive suppliers have to develop innovating systems inorder to reduce greenhouse gas rejects produce by vehicles. The new mild-hybrid electronic applications require the development of new strategies due to their integration and the reduction of power losses.Thereby, a proposition consisted in creating power modules constituted by MOSFETs characterized by alow blocking voltage under high current. The starter alternator reversible application also named “Stop &Start” requires robust and reliable components in order to support a high current solicitation in avalanche mode for temperatures up to 175°C.Research work presented in this thesis concerns the robustness and reliability enhancement of MOSFET components. First of all, the important part is about avalanche mode understanding and their issues. Inthis context, the fabrication process is a main part for quality and reliability requirements. Then, the workis focused on gate oxide process quality in order to hold gate-source and gate-drain stress modes.Moreover, the development of an innovating test at wafer level derivate from QBD test, allowed the precise evaluation of process modification thanks to the correlation with reliability campaign results. Finally, theMOSFET life cycle needs a quality monitoring constituted by two main steps. The first one is the monitoring of electrical parameters in time with a post-processing statistical analysis. The second one is the use of a traceability tool between the power module and the silicon die in order to highlight possible defects in the final starter alternator application, and understand failure root causes. The innovations presented in this thesis are included in the continued improvement approach for MOSFETs quality and robustness enhancement.

In the modern semiconductor world, there is a significant scaling of the transistor dimensions--The transistor gate length and the gate oxide thickness drop down to only several nanometers. Today the semiconductor industry is already dominated by submicron devices and other material devices for the high transistor density and performance enhancement. In this case, the semiconductor reliability issues are the most important thing for commercialization. The major reliability issues caused by voltage are hot carrier effects (HCs) and gate oxide breakdown (BD) effects. These issues are recently more important to industry, due to the small size and high lateral field in short-channel of the device will cause high electrical field and other reliability issues. This dissertation primarily focuses on the study of the CMOS device gate oxide breakdown effect on different kinds of circuits performance, also some HC effects on circuit's performance are studied. The physical mechanisms for BD have been presented. A practical and accurate equivalent breakdown circuit model for the CMOS device was studied to simulate the RF performance degradation on the circuit level. The BD location effect has been evaluated. Furthermore, a methodology was developed to predict the BD effects on the circuit's performances with different kinds of BD location. It also provides guidance for the reliability considerations of the digital, analog, and RF circuit design. The BD effects on digital circuits SRAM, analog circuits Sample&Hold, and RF building blocks with the nanoscale device--low noise amplifier, LC oscillator, mixer, and power amplifier, have been investigated systematically. Finally 90 nm device will be used to study the HC effect on the circuit's performance. The contributions of this dissertation include: Providing a thorough study of the gate oxide breakdown issues caused by the voltage stress on the device--from device level to circuit level; Studying real voltage stress case--high frequency (950 MHz) dynamic stress, and comparing with the traditional DC stress; A simple, practical, and analytical method is derived to study the gate oxide breakdown effect including breakdown location effect and soft / hard breakdown on the digital, analog and RF circuits performances. A brief introduction and simulation for 90 nm device HC effect provide some useful information and helpful data for the industry. The gate oxide breakdown effect is the most common device reliability issue. The successful results of this dissertation, from device level to circuit level, provide an insight on how the BD affects the circuit's performance, and also provide some useful data for the circuit designers in their future work.

Silicon is the main material used in electronics. The evolution of power electronics and the need for more power efficient semiconductor devices led silicon to its limits. Silicon carbide is a promising material for electronic applications with a wide band-gap, high critical electric field, high thermal conductivity and saturation velocity. Except from its superiority to silicon, silicon carbide comes with a drawback of about two orders of magnitude more interface traps in the SiC/SiO2 interface compared with silicon. A result of this drawback is a flat-band voltage shift when applying a stress to the gate of MOS capacitors and power MOSFETs. In order to study the pure characteristics of the SiC/SiO2 interface, two stress methods, a current pulse stress and gate voltage upsweep, have been applied on 4H-SiC capacitors with nitrided thermal oxides at room temperature and at higher temperatures. The flat-band voltage recovery was examined. The flat-band voltage could be restored at room temperature with a gate voltage downsweep while a restoration is not needed at higher temperatures. The maximum voltage (initial voltage) and the voltage rate of the downsweep were investigated and higher initial voltages and lower voltage rates showed to lead to better VFB restoration. A 200 millisecond long current pulse stress was implemented and it had almost similar effects as the voltage upsweep which lasts 50 seconds. / Kisel är det viktigaste materialet som används i elektronik. Utvecklingen av kraftelektronik och behovet av mer energieffektiva halvledarkomponenter ledde kisel till sina gränser. Kiselkarbid är ett lovande material för elektroniska applikationer med ett brett bandgap, högt kritiskt elektriskt fält, hög värmeledningsförmåga och hög mättningshastighet. Förutom dess överlägsenhet gentemot kisel, kommer kiselkarbid med en nackdel med cirka två storleksordningar fler gränssnittsfällor i SiC / SiO2-gränssnittet jämfört med kisel. Ett resultat av denna nackdel är en förskjutning av flatbands-spänningen, VFB, när man applicerar en spänning på gaten till MOS-kondensatorer och kraft- MOSFETar. För att studera de rena egenskaperna hos SiC/SiO2-gränssnittet har två spänningsmetoder, en strömpulsstress och ett uppåtriktat gate-spänningssvep, applicerats på 4H-SiC- kondensatorer med nitriderade termiska oxider vid rumstemperatur och vid högre temperaturer. Återställning av VFB undersöktes. VFB kan återställas vid rumstemperatur med ett nedåtriktat gate-spänningssvep medan en återställning inte behövs vid högre temperaturer. Den maximala spänningen (initialspänningem) och svephastigheten för det nedåtriktade svepet undersöktes och högre initialspänningar och lägre svephastigheter visade sig leda till bättre VFB-återställning. En 200 millisekund lång strömpuls-stress implementerades och den hade nästan samma effekter som ett uppåtriktat spänningssvep

This study investigated the Class-E power amplifier operating at 5.2 GHz. Since the operation of this amplifier applies a lot of stress on the switching transistor, a cascode topology was applied in order to reduce the drain-source voltage stress. Such an amplifier was designed and optimized in order to improve stability, power added efficiency, and matching. A layout for the said design was then created to be fabrication-ready using the TSMC 0.18 um technology. Post-layout simulations were performed in order to realize a more realistic circuit performance with the layout design in mind. Long-term stress effects, such as oxide breakdown, on the key transistors were modeled and simulated in order to achieve an understanding of how leakage currents affect the overall circuit performance. Simulated results were compared and contrasted against theoretical understanding using derived equations. Recommendations for future advancements were made for modification and optimization of the circuit by the application of other stress reduction strategies, variation in the class-E topology, and improvement of the driver stage.

Apresentamos neste trabalho um estudo do efeito da depleção do silício policristalino e da corrente de tunelamento em dispositivos com óxidos de porta finos. Utilizamos curvas características da capacitância em função da tensão de porta (C-V), para analisar a degradação causada por estes efeitos.Quanto ao efeito da depleção do silício policristalino a capacitância total na região de inversão apresenta uma redução conforme a concentração de dopantes do silício policristalino diminui. Este efeito foi observado em curvas C-V tanto de alta como de baixa freqüência, sendo esta última mais afetada. A corrente de tunelamento através do óxido de porta apresentou uma influência na largura da região de depleção no silício, que aumentou devido ao tunelamento de portadores do substrato. Como resultado, uma diminuição na capacitância do silício foi observada, fazendo a curva C-V diminuir na região de inversão. Quando considerado o efeito de depleção no silício policristalino junto com o efeito do tunelamento, observou-se que na região da porta houve um excesso de portadores, causando uma diminuição na região de depleção do silício policristalino. Neste caso a curva C-V sofreu uma maior redução, tornando-se difícil separar os dois efeitos. A curva C-V de baixa freqüência foi a mais atingida, pois como os portadores tem tempo de resposta, pode-se observar a influência da corrente de tunelamento nas cargas de inversão. Apresentamos ainda um novo método para a determinação da concentração de dopantes no substrato e no silício policristalino, através de curvas C-V de alta freqüência. Simulações numéricas bidimensionais e medidas experimentais foram utilizadas para validação do método. Os resultados obtidos indicam que o método proposto apresenta um grande potencial, tendo como principal vantagem a simplicidade de aplicação. / In this work we present the study of polysilicon depletion and the gate tunneling current effects in thin-gate oxide devices. Characteristic curves of capacitance as a function of the gate voltage (C-V) were used to analyze the degradation caused for these effects. Regarding the poly depletion effect, a reduction of the total capacitance in the inversion region was verified as the polysilicon doping concentration decreases. This effect was observed in C-V curves in high and low frequency, being the last one more affected. The gate tunneling current presented an influence on the width of the depletion silicon region, which increased due to the carriers tunneling from the substrate. As a result, a reduction in the silicon capacitance was observed, causing the C-V curve reduction in the inversion region. When the polysilicon depletion effect is considered together with the tunneling effect, it was observed that there is a carriers excess in the gate region, causing a reduction of the polysilicon depletion region width. In this case, the C-V curve suffered a larger reduction, making difficult to separate both effects. The most affected characteristic was the C-V curve at low frequency, due to existence of the carrier response time that allows observing the influence of the tunneling current in inversion charges. A new method for the determination of the doping concentration of substrate and polysilicon was also presented, through C-V curves at high frequency. Two-dimensional simulations and experimental measurements were used to validate the method. The obtained results indicate that the propose method present a higher potential, having as principal advantage the simplicity of application.

Apresentamos neste trabalho um estudo do efeito da depleção do silício policristalino e da corrente de tunelamento em dispositivos com óxidos de porta finos. Utilizamos curvas características da capacitância em função da tensão de porta (C-V), para analisar a degradação causada por estes efeitos.Quanto ao efeito da depleção do silício policristalino a capacitância total na região de inversão apresenta uma redução conforme a concentração de dopantes do silício policristalino diminui. Este efeito foi observado em curvas C-V tanto de alta como de baixa freqüência, sendo esta última mais afetada. A corrente de tunelamento através do óxido de porta apresentou uma influência na largura da região de depleção no silício, que aumentou devido ao tunelamento de portadores do substrato. Como resultado, uma diminuição na capacitância do silício foi observada, fazendo a curva C-V diminuir na região de inversão. Quando considerado o efeito de depleção no silício policristalino junto com o efeito do tunelamento, observou-se que na região da porta houve um excesso de portadores, causando uma diminuição na região de depleção do silício policristalino. Neste caso a curva C-V sofreu uma maior redução, tornando-se difícil separar os dois efeitos. A curva C-V de baixa freqüência foi a mais atingida, pois como os portadores tem tempo de resposta, pode-se observar a influência da corrente de tunelamento nas cargas de inversão. Apresentamos ainda um novo método para a determinação da concentração de dopantes no substrato e no silício policristalino, através de curvas C-V de alta freqüência. Simulações numéricas bidimensionais e medidas experimentais foram utilizadas para validação do método. Os resultados obtidos indicam que o método proposto apresenta um grande potencial, tendo como principal vantagem a simplicidade de aplicação. / In this work we present the study of polysilicon depletion and the gate tunneling current effects in thin-gate oxide devices. Characteristic curves of capacitance as a function of the gate voltage (C-V) were used to analyze the degradation caused for these effects. Regarding the poly depletion effect, a reduction of the total capacitance in the inversion region was verified as the polysilicon doping concentration decreases. This effect was observed in C-V curves in high and low frequency, being the last one more affected. The gate tunneling current presented an influence on the width of the depletion silicon region, which increased due to the carriers tunneling from the substrate. As a result, a reduction in the silicon capacitance was observed, causing the C-V curve reduction in the inversion region. When the polysilicon depletion effect is considered together with the tunneling effect, it was observed that there is a carriers excess in the gate region, causing a reduction of the polysilicon depletion region width. In this case, the C-V curve suffered a larger reduction, making difficult to separate both effects. The most affected characteristic was the C-V curve at low frequency, due to existence of the carrier response time that allows observing the influence of the tunneling current in inversion charges. A new method for the determination of the doping concentration of substrate and polysilicon was also presented, through C-V curves at high frequency. Two-dimensional simulations and experimental measurements were used to validate the method. The obtained results indicate that the propose method present a higher potential, having as principal advantage the simplicity of application.