Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, March 2005. / Thesis Advisor(s): Douglas J. Fouts. Includes bibliographical references (p. 61). Also available online.

Thesis (M.S.)--Rochester Institute of Technology, 1993. / Typescript. Includes bibliographical references.

Thesis (M.S.)--Rochester Institute of Technology, 2009. / Typescript. Includes bibliographical references (leaf 45).

Thesis (M.E.)--University of Canterbury, 2006. / Typescript (photocopy). "March 2006." Includes bibliographical references (p. 145-151). Also available via the World Wide Web.

Ο σκοπός της παρούσας Διπλωματικής Εργασίας είναι η μελέτη και η υλοποίηση ενός 8085 προσομοιωτή σε FPGAs με τη χρήση VHDL. H υλοποίηση έγινε με την βοήθεια του περιβάλλοντος εξομοίωσης του Quartus v7.2 της ALTERA, με την χρήση της γλώσσας VHDL [8],[10].Η εργασία αυτή χωρίζεται σε 12 κεφάλαια: Στο πρώτο κεφάλαιο γίνεται αναφορά στο μικροεπεξεργαστή και στα τεχνικά του γνωρίσματα [1], [2], [4]. Στο δεύτερο κεφάλαιο γίνεται μια εκτενής αναφορά στη γλώσσα VHDL [3], [10]. Στο τρίτο κεφάλαιο παρουσιάζεται η αναπτυξιακή πλατφόρμα DE2 της εταιρίας ALTERA. Παρουσιάζονται αναλυτικά οι δυνατότητες και τα σχεδιαστικά χαρακτηριστικά της αναπτυξιακής κάρτας DE2 της ALTERA καθώς και τεχνική απεικόνισης video με τη χρήση FPGA [3], [9], [14]. Στο τέταρτο κεφάλαιο αναλύεται η λειτουργία του πρώτου μεγάλου τμήματος του μικροεπεξεργαστή, της ALU. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του κυκλώματος, η λειτουργία κάθε επιμέρους τμήματος καθώς και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [5], [6], [12], [13]. Στο πέμπτο κεφάλαιο αναλύεται η λειτουργία του register file. Πρόκειται για το τμήμα των καταχωρητών, το οποίο είναι υπεύθυνο για την μεταφορά δεδομένων και την λειτουργία των διαύλων διευθύνσεων. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του κυκλώματος, η λειτουργία κάθε επιμέρους τμήματος καθώς και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [5], [7], [11], [13], [14]. Στο έκτο κεφάλαιο αναλύεται η λειτουργία του τμήματος ελέγχου διακοπών. Πρόκειται για το τμήμα το οποίο εξυπηρετεί οποιαδήποτε αίτηση για διακοπή και το οποίο έχει οριστεί να είναι υπεύθυνο και για την σειριακή επικοινωνία. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του κυκλώματος, η λειτουργία κάθε επιμέρους τμήματος καθώς και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [1], [12], [13]. Στο έβδομο κεφάλαιο γίνεται μια πρώτη απόπειρα σύνδεσης των τριών πρώτων μεγάλων τμημάτων του μικροεπεξεργαστή [12], [13]. Στο όγδοο κεφάλαιο αναλύεται η λειτουργία της control unit ως μονάδα ελέγχου και διαχείρισης των σημάτων ελέγχου του όλου κυκλώματος του μικροεπεξεργαστή. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του κυκλώματος, η λειτουργία κάθε επιμέρους τμήματος καθώς και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [5], [7], [12], [13]. Στο ένατο κεφάλαιο παρουσιάζεται το κύκλωμα του μικροεπεξεργαστή μέσα από την σύνδεση των επιμέρους τμημάτων του. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [7], [12], [13]. Στο δέκατο κεφάλαιο παρουσιάζεται ο μικροπρογραμματισμός της microprogram ROM της control unit. Αναλύεται διεξοδικά η λειτουργία των σημάτων ελέγχου των τμημάτων του μικροεπεξεργαστή για την εκτέλεση κάθε μιας εντολής του 8085 [7], [12], [13]. Στο ενδέκατο κεφάλαιο γίνεται εξομοίωση ορισμένων προγραμμάτων για τον έλεγχο της ορθής λειτουργίας των εντολών και των σημάτων ελέγχου και εξόδου του μικροεπεξεργαστή 8085 [1], [12], [13]. Στο δωδέκατο κεφάλαιο παρουσιάζεται η υλοποίηση του μικροεπεξεργαστή στην αναπτυξιακή πλατφόρμα DE2 της εταιρείας ALTERA [3], [14]. Τελειώνοντας θα ήθελα να ευχαριστήσω τον επιβλέποντα της προσπάθειας αυτής Αναπληρωτή Καθηγητή κ. Ευάγγελο Ζυγούρη, η καθοδήγηση του οποίου υπήρξε καθοριστική. / The purpose of this thesis is the design of an 8085 emulator in FPGAs using VHDL. The implementation was done with the simulation environment of ALTERA Quartus v7.2, using VHDL. The project is divided into 12 chapters: The first chapter refers to the 8085 microprocessor and it’s technical features [1], [2], [4]. The second chapter is a detailed presentation of the VHDL language [3], [10]. The third chapter presents DE2 development board of Altera. Capabilities and design features of DE2 board are presented and vga video display generation using FPGAs is explained [3], [9], [14]. The fourth chapter analyzes the operation of the first large section of the microprocessor, ALU. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [5], [6], [12], [13]. The fifth chapter presents the operation of the register file. Register File is responsible for data transfer and operation of the address bus. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [5], [7], [11], [13], [14]. The sixth chapter presents microprocessor 's interrupts. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [1], [12], [13]. The seventh chapter is a first attempt to link the first three major sections of the microprocessor [12], [13]. The eighth chapter presents the operation of the control unit. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [5], [7], [12], [13]. The ninth chapter presents the circuit of the microprocessor through the connection of all individual parts. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [7], [12], [13]. The tenth chapter presents the microprogramming of microprogram ROM of the control unit. It analyzes in detail the operation of the control signals of the parts of the microprocessor to perform each of 8085 command [7], [12], [13]. The eleventh chapter presents the simulation of microprocessor through assembly programs written in RAM memory of 8085 microprocessor [1], [12], [13]. The twelfth chapter presents the implementation of microprocessor in FPGAs using DE2 development board of Altera [3], [14].

Orientadores: Sandro Rigo, Guido Costa Souza de Araujo / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-13T11:44:55Z (GMT). No. of bitstreams: 1 Costa_RichardMaciel_M.pdf: 4274440 bytes, checksum: 4094fea059358a9a5eb39c56aa5f1f3c (MD5) Previous issue date: 2008 / Resumo: Em um passado recente os sistemas eram constituídos de partes discretas tais como microprocessadores, memórias e Application Specific Integrated Circuits (ASICs). Essa separação clara e simples tornava possível a especificação ser feita por uns poucos projetistas utilizando uma abordagem top-down: a partir de um modelo comportamental ou Register-Transfer Level (descritos em VHDL, por exemplo), progressivamente refinando o modelo ate o nível Transistor-to-Transistor. Entretanto, o avanço contínuo do processo de miniaturização de transistores possibilitou a criação de sistemas completos integrados em um único chip (também chamados de System-on-chip). Dado que esses sistemas s~ao tipicamente constituídos por diversos componentes complexos, um nível mais alto de abstração - o de sistema - foi criado, juntamente com suas linguagens associadas (como a linguagem SystemC), para facilitar o trabalho dos projetistas. As linguagens utilizadas para modelar no nível de sistema são diferentes das linguagens utilizadas para modelar nos níveis comportamental e Register-Transfer. Assim, surge o problema de como co-verificar componentes descritos em diferentes níveis de abstração; característica desejável para projetos de grande porte, já que fornece uma garantia de interoperabilidade entre os componentes no sistema final. Este trabalho, então, apresenta uma metodologia para resolver o problema de co-simulação entre a linguagem de descrição de hardware VHDL e a linguagem de descrição de sistema SystemC através do uso da Verilog Procedural Interface (VPI). Alem da metodologia em si, descreve-se o trabalho no sentido de criar um arcabouço para validar a metodologia e testes comparativos entre a implementação feita e uma ferramenta comercial popular. / Abstract: In a recent past, systems were mostly constituted by well-separated parts such as microprocessors, memories and Application Specific Integrated Circuits (ASICs). That simple and clear organization allowed entire systems to be designed by only a few designers through a top-down approach: from the behavioral or register transfer model (using VHDL, for instance) advancing to the transistor-to-transistor level. However, the continuous advance of the process of shrinking transistors made it possible to create entire systems integrated in a single die (called System-on-chip). Because these systems are usually constituted by many complex components, a higher abstraction level - the system level - was created, together with the associated languages, to ease the work of the designers. The languages used to model on the system level are diferent from the languages used to model on the behavioral and register-transfer levels. Therefore, the problem of how to co-verify components written in diferent abstraction levels arises; this co-verification is desirable for big projects, since it provides a way to check if the components of the target system are working together. This project presents a methodology to solve the co-simulation problem between the hardware description language VHDL and the system description languagem SystemC through the use of the Verilog Procedural Interface (VPI). We describe the methodology and also describe the framework used to validate the methodology and comparative tests between this framework and a well-known comercial tool. / Mestrado / Arquitetura de Computadores / Mestre em Ciência da Computação

Orientador: Euripedes Guilherme de Oliveira Nobrega / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Mecanica / Made available in DSpace on 2018-08-15T01:47:19Z (GMT). No. of bitstreams: 1 Oliveira_AlexandreTomazati_M.pdf: 3226409 bytes, checksum: 06c44b66428a69ae6b8214fd07432ae6 (MD5) Previous issue date: 2009 / Resumo: O eletrocardiograma (ECG) é uma ferramenta utilizada para o diagnóstico de cardiopatias e outras doenças. Este trabalho tem como objetivo a detecção do complexo QRS, com foco na onda R, que representa a contração dos ventrículos. Para isso, são apresentadas duas técnicas de processamento do sinal de ECG. A primeira utiliza o algoritmo proposto por Pan & Tompkins que consiste em um banco de filtros digitais. A segunda faz uso da transformada wavelet discreta, que permite a localização de características de sinais tanto no tempo quanto na frequência. É apresentado um comparativo da eficácia dos dois algoritmos com base na sua implementação através de FPGA, utilizando dois métodos, o processamento serial em microcontrolador programado em C e o paralelo inteiramente em VHDL, com o intuito de comparar os tempos de processamento. Os resultados sugerem que trabalhos futuros poderão ser baseados na investigação de outras famílias wavelets para a detecção do complexo QRS em sinais de ECG, bem como explorar outros métodos de implementação de filtros em FPGA. / Abstract: The electrocardiogram (ECG) is a tool used for diagnosis of diseases related to the heart. This work has the purpose of detecting QRS complex, focusing on the R wave, which represents the ventricles'contraction. It is presented two techniques of processing ECG signals. The first uses Pan & Tompkins algorithm based on digital filtering. The second uses the discrete wavelet transform, which represents the characteristics of the signal simultaneously in time and frequency. It is presented a comparison of the efficacy of both algorithms, which are implemented in FPGA, using serial processing based on a C programmed microcontroller, and parallel processing entirely in VHDL, with the purpose of comparing the time of processing. The results suggest that future work can be based on the investigation of other wavelets family for detecting QRS complex in ECG signals and other methods of implementing filters in FPGA. / Mestrado / Mecanica dos Sólidos e Projeto Mecanico / Mestre em Engenharia Mecânica

GPU-based heterogeneous system architectures are popular as they combine the advantages of CPU with the benefits of GPU. Development of high-performance and power-efficient software for heterogeneous system architecture needs to take both hardware and software specifications into consideration, which leads the software development process to be more complicated. To simplify the software development process, Architecture Description Languages (ADLs) came out. By modeling the target architecture components into structural formats, programmers can adapt their software to the platforms which they used. XPDL is a modular and extensible XML-based platform description language which is mainly designed to support optimization.The purposes of this thesis are to design the query API (Application Programming Interface) and develop a compiler which translates the XPDL descriptors to libraries that implement the API to support programmers for the development of adaptive high-performance and energy-optimized software. In this thesis, we design and develop a compiler to generate the API according to the XPDL descriptors.The main workflow of the designed compiler is following: first, the toolchain validates the XPDL descriptors against XSDs. Second, it parses the descriptors into DOM trees and transforms them into XPDL model trees. Next, the compiler links all XPDL model trees together, which results in the intermediate representation (IR). Then, any unspecified node values which means the unknown attributes, are handled by microbenchmark generator and executor. In the end, the code generator generates the libraries which expose the API according to the information in the IR. Finally, a few example codes are discussed to show how the API can be used to develop performance adaptive applications on heterogeneous systems.

Field Programmable Gate Arrays (FPGAs) offer a new opportunity for computer vision algorithms. By implementing in Very High Speed Integrated Circuit Hardware Description languate (VHDL), algorithms can be developed quickly, while being running much faster than by using conventional Von Neumann machines (such as a Personal Computer or Macintosh). The process of creating a working design from an algorithm is described in detail, and we present experimental results obtained from such a process for Sobel edge detection, as well as modifications for techniques for background modeling and fire detection.

This thesis discusses an algorithm for mapping conceptual graphs to primitive VHDL processes. The behavior of each primitive process is stored in the form of a schema. The algorithm identifies concepts in the input referring to MODAS (Modeler's Assistant) process primitives and maps their schemata to the input conceptual graph. The results of the mapping are used to modify the primitive process's VHDL and instantiate a new process. A library of schemata for the primitive processes in MODAS has been developed. This algorithm has been implemented in the CGVHDL Linker program. It has improved the capability of the CGVHDL Linker to handle more complex design specifications. The algorithm provides the CGVHDL Linker with the ability to interpret a structure in the input conceptual graph. It also eases the burden on the designer who can refer to some components without giving details of their behavior. / Master of Science