No description available.

No description available.

No description available.

As power conversion technology is being integrated further into high-reliability environments such as aerospace and electric vehicle applications, a full analysis and understanding of the system's robustness under operating conditions inside and outside the safe-operating-area is necessary. The robustness of power semiconductor devices, a primary component of power converters, has been traditionally evaluated through qualification tests that were developed for legacy silicon (Si) technologies. However, new devices have been commercialized using wide bandgap (WBG) semiconductors including silicon carbide (SiC) and gallium nitride (GaN). These new devices promise enhanced capabilities (e.g., higher switching speed, smaller die size, lower junction capacitances, and higher thermal conductance) over legacy Si devices, thus making the traditional qualification experiments ineffective. This work begins by introducing a new methodology for evaluating the switching robustness of SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). Recent static acceleration tests have revealed that SiC MOSFETs can safely operate for thousands of hours at a blocking voltage higher than the rated voltage and near the avalanche boundary. This work evaluates the robustness of SiC MOSFETs under continuous, hard-switched, turn-off stresses with a dc-bias higher than the device rated voltage. Under these conditions, SiC MOSFETs show degradation in merely tens of hours at 25si{textdegree}C and tens of minutes at 100si{textdegree}C. Two independent degradation and failure mechanisms are unveiled, one present in the gate-oxide and the other in the bulk-semiconductor regions, detected by the increase in gate leakage current and drain leakage current, respectively. The second degradation mechanism has not been previously reported in the literature; it is found to be related to the electron hopping along the defects in semiconductors generated in the switching tests. The comparison with the static acceleration tests reveals that both degradation mechanisms correlate to the high-bias switching transients rather than the high-bias blocking states. The GaN high-electron-mobility transistor (HEMT) is a newer WBG device that is being increasingly adopted at an unprecedented rate. Different from SiC MOSFETs, GaN HEMTs have no avalanche capability and withstand the surge energy through capacitive charging, which often causes significant voltage overshoot up to their catastrophic limit. As a result, the dynamic breakdown voltage (BV) and transient overvoltage margin of GaN devices must be studied to fully evaluate the switching ruggedness of devices. This work characterizes the transient overvoltage capability and failure mechanisms of GaN HEMTs under hard-switched turn-off conditions at increasing temperatures, by using a clamped inductive switching circuit with a variable parasitic inductance. This test method allows flexible control over both the magnitude and the dV/dt of the transient overvoltage. The overvoltage robustness of two commercial enhancement-mode (E-mode) p-gate HEMTs was extensively studied: a hybrid drain gate injection transistor (HD-GIT) with an Ohmic-type gate and a Schottky p-Gate HEMT (SP-HEMT). The overvoltage failure of the two devices was found to be determined by the overvoltage magnitude rather than the dV/dt. The HD-GIT and the SP-HEMT were found to fail at a voltage overshoot magnitude that is higher than the breakdown voltage in the static current-voltage measurement. These single event failure tests were repeated at increasing temperatures (100si{textdegree}C and 150si{textdegree}C), and the failures of both devices were consistent with room temperature results. The two types of devices show different failure behaviors, and the underlying mechanisms (electron trapping) have been revealed by physics-based device simulations. Once this single-event overvoltage failure was established, the device's robustness under repetitive overvoltage and surge-energy events remained unclear; therefore, the switching robustness was evaluated for both the HD-GIT and SP-HEMT in a clamped, inductive switching circuit with a 400 V dc bias. A parasitic inductance was used to generate the overvoltage stress events with different overvoltage magnitude up to 95% of the device's destructive limit, different switching periods from 10 ms to 0.33 ms, different temperatures up to 150si{textdegree}C, and different negative gate biases. The electrical parameters of these devices were measured before and after 1 million stress cycles under varying conditions. The HD-GITs showed no failure or permanent degradation after 1-million overvoltage events at different switching periods, or elevated temperatures. The SP-HEMTs showed more pronounced parametric shifts after the 1 million cycles in the threshold voltage, on-resistance, and saturation drain current. Different shifts were also observed from stresses under different overvoltage magnitudes and are attributable to the trapping of the holes produced in impact ionization. All shifts were found to be recoverable after a relaxation period. Overall, the results from these switching-oriented robustness tests have shown that SiC MOSFETs show a tremendous lifetime under static dc-bias experiments, but when excited by hard-switching turn-off events, the failure mechanisms are accelerated. These results suggest the insufficient robustness of SiC MOSFETs under high bias, hard switching conditions, and the significance of using switching-based tests to evaluate the device robustness. These inspired the GaN-based hard-switching turn-off robustness experiments, which further demonstrated the dynamic breakdown voltage phenomena. Ultimately these results suggest that the breakdown voltage and overvoltage margin of GaN HEMTs in practical power switching can be significantly underestimated using the static breakdown voltage. Both sets of experiments provide further evidence for the need for switching-oriented robustness experiments to be implemented by both device vendors and users, to fully qualify and evaluate new power semiconductor transistors. / Doctor of Philosophy / Power conversion technology is being integrated into industrial and commercial applications with the increased use of laptops, server centers, electric vehicles, and solar and wind energy generation. Each of these converters requires the power semiconductor devices to convert energy reliably and safely. textcolor{black}{Silicon has been the primary material for these devices; however,} new devices have been commercialized from both silicon carbide (SiC) and gallium nitride (GaN) materials. Although these devices are required to undergo qualification testing, the standards were developed for silicon technology. The performance of these new devices offers many additional benefits such as physically smaller dimensions, greater power conversion efficiency, and higher thermal operating capabilities. To facilitate the increased integration of these devices into industrial applications, greater robustness and reliability analyses are required to supplement the traditional tests. The work presented here provides two new experimental methodologies to test the robustness of both SiC and GaN power transistors. These methodologies are oriented around hard-switching environments where both high voltage biases and high conduction current exist and stress the intrinsic semiconductor properties. Experimental evaluations were conducted of both material technologies where the electrical properties were monitored over time to identify any degradation effects. Additional analyses were conducted to determine the physics-oriented failure mechanisms. This work provides insight into the limitations of these semiconductor devices for both device designers and manufacturers as well as power electronic system designers.

Transfer signal without wire has been widely accepted after the introduction of cellular technology and WiFi technology, hence the power cable is the last wire that has yet to be eliminated. Inductive power transfer (IPT) has drawn substantial interest in both academia and industry due to its advantages including convenience, nonexistence of cable and connector, no electric shock issue, ability to work under some extreme environment, and so on. After performing thorough literature review of IPT systems, two major drawbacks including low power efficiency and coil displacement sensitivity are identified as the main obstacles that have to be solved in order for these systems to reach full functionality and compete with existing wired solutions. To address the limitations and design challenges in the IPT systems, a detailed electric circuit modeling of individual part of the IPT DC-DC stage is performed. Several resonant DC-AC inverters and output AC-DC rectifiers are compared based on their performance and feasibility in inductive charging applications. Different equivalent circuit models for the loosely coupled transformer (LCT) are derived which allows for better understanding on how power is distributed among the circuit components. Five compensation networks to improve the power transfer efficiency are evaluated and their suitable application occasions are identified. With comprehensive circuit model analysis, the influence of the resonant compensation tank parameters has been investigated carefully for efficient power transfer. A novel tuning network parameters design methodology is proposed based on multiple given requirement such as battery charging profile, geometry constraints and operating frequency range, with the aim of avoiding bifurcation phenomenon during the whole charging process and achieving decent efficiency. A 4-kW hardware prototype based on the proposed design approach is built and tested under different gap and load conditions. Peak IPT system DC-DC efficiencies of 98% and 96.6% are achieved with 4-cm and 8-cm air gap conditions, which is comparable to the conventional plug-in type or wired charging systems for EVs. A long-hour test with real EV batteries is conducted to verify the wireless signal transmission and CC/CV mode seamless transition during the whole charging profile without bifurcation. To reduce the IPT system sensitivity to the gap variation or misalignment, a novel LCT design approach without additional complexity for the system is proposed. With the aid of FEA simulation software, the influence of coil relative position and geometry parameters on the flux distribution and coupling coefficient of the transmitter and receiver is studied from an electromagnetic perspective. An asymmetrical LCT based on the proposed design method is built to compare with a traditional symmetrical LCT. With fixed 10-mm gap and 0 to 40-mm misalignment variation, the coupling coefficient for the symmetrical LCT drops from 0.354 to 0.107, and the corresponding efficiency decrease is 16.6%. The operating frequency variation is nearly 100 kHz to maintain same input/output condition. When employing the proposed asymmetrical LCT, the coupling coefficient changes between 0.312 and 0.273, and the maximum efficiency deviation is kept within 0.67% over the entire 40-mm misalignment range. Moreover, the required frequency range to achieve same operation condition is less than 10 kHz. Lastly, some design considerations to further improve the IPT system efficiency are proposed on the basis of the designed asymmetrical LCT geometry. For given circuit specifications and LCT coupling conditions, determination of the optimal primary winding turns number could help achieve minimal winding loss and core loss. For lower output power, the optimal primary winding turns number tends to be larger compared to that for higher output power IPT system. Two asymmetrical LCT with similar dimension but different number of turns are built and tested with a 100-W hardware prototype for laptop inductive charging. The proposed efficiency improvement methodology is validated by the winding loss and core loss from experimental results. / Ph. D.

Relations among various nodes in the circuit, as captured by static and inductive invariants, have shown to have a positive impact on a wide range of EDA applications. Techniques such as boolean constraint propagation for static learning and assume-then-verify approach to reason about inductive invariants have been possible due to efficient SAT solvers. Although a significant amount of research effort has been dedicated to the development of effective invariant learning techniques over the years, the computation time for deriving powerful multi-node invariants is still a bottleneck for large circuits. Fast computation of static and inductive invariants is the primary focus of this thesis. We present a novel technique to reduce the cost of static learning by intelligently identifying redundant computations that may not yield new invariants, thereby achieving significant speedup. The process of inductive invariant reasoning relies on the assume-then-verify framework, which requires multiple iterations to complete, making it infeasible for cases with a large set of multi-node invariants. We present filtering techniques that can be applied to a diverse set of multi-node invariants to achieve a significant boost in performance of the invariant checker. Mining and reasoning about all possible potential multi-node invariants is simply infeasible. To alleviate this problem, strategies that narrow down the focus on specific types of powerful multi-node invariants are also presented. Experimental results reflect the promise of these techniques. As a measure of quality, the invariants are utilized for untestable fault identification and to constrain ATPG for path delay fault testing, with positive results. / Master of Science

Verification is an important step for Integrated Circuit (IC) design. In fact, literature has reported that up to 70% of the design effort is spent on checking if the design is functionally correct. One of the core verification tasks is Equivalence Checking (EC), which attempts to check if two structurally different designs are functionally equivalent for all reachable states. Powerful equivalence checking can also provide opportunities for more aggressive logic optimizations, meeting different goals such as smaller area, better performance, etc. The success of Combinational Equivalence Checking (CEC) has laid a foundation to industry-level combinational logic synthesis and optimization. However, Sequential Equivalence Checking (SEC) still faces much challenge, especially for those complex circuits that have different state encodings and few internal signal equivalences. In this thesis, we propose a novel simulation-based multi-node inductive invariant generation and pruning technique to check the equivalence of sequential circuits that have different state encodings and very few equivalent signals between them. By first grouping flip-flops into smaller subsets to make it scalable for large designs, we then propose a constrained logic synthesis technique to prune potential multi-node invariants without inadvertently losing important constraints. Our pruning technique guarantees the same conclusion for different instances (proving SEC or not) compared to previous approaches in which merging of such potential invariants might lose important relations if the merged relation does not turn out to be a true invariant. Experimental results show that the smaller invariant set can be very effective for sequential equivalence checking of such hard SEC instances. Our approach is up to 20x-- faster compared to previous mining-based methods for larger circuits. / Master of Science

Surge-energy robustness is essential for power devices in many applications such as automotive powertrains and electricity grids. While Si and SiC MOSFETs can dissipate surge energy via avalanche, the GaN high-electron-mobility transistor (HEMT) has no avalanche capability and withstands surge energy by its overvoltage capability. However, a comprehensive study into the surge-energy robustness of the cascode GaN HEMT, a composite device made of a GaN HEMT and a Si metal-oxide-semiconductor field-effect-transistor (MOSFET), is still lacking. This work fills this gap by investigating the failure and degradation of 650-V-rated cascode GaN HEMTs in single-event and repetitive unclamped inductive switching (UIS) tests. The cascode was found to withstand surge energy by the overvoltage capability of the GaN HEMT, accompanied by an avalanche in the Si MOSFET. In single-event UIS tests, the cascode failed in the GaN HEMT at a peak overvoltage of 1.4~1.7 kV, which is statistically lower than the device's static breakdown voltage (1.8~2.2 kV). In repetitive UIS tests, the device failure boundary was found to be frequency-dependent. At 100 kHz, the failure boundary (~1.3 kV) was even lower than the single-event UIS boundary. After 1 million cycles of 1.25-kV UIS stresses, devices showed significant but recoverable parametric shifts. Physics-based device simulation and modeling were then performed to understand the circuit test results. The electron trapping in the buffer layer of the GaN HEMT can explain all the above failure and degradation behaviors in the GaN HEMT and the resulted change in its dynamic breakdown voltage. Moreover, the GaN buffer trapping is believed to be assisted by the Si MOSFET avalanche. An analytical model was also developed to extract the charges and losses produced in the Si avalanche in a UIS cycle. These results provide new insights into the surge-energy and overvoltage robustness of cascode GaN HEMTs. / M.S. / Power conversion technologies are now inseparable in industrial and commercial applications with widespread solar panels, laptops, data centers, and electric vehicles. Power devices are the critical components of power conversion systems. Since the introduction of Si power metal-oxide-semiconductor field-effect-transistor (MOSFET) in the mid-1970s, it has become the go-to device that enables efficient and reliable power conversion. After decades of practice on Si MOSFET, the device performance has reached the theoretical limit of the Si material. The recent introduction of wide-bandgap (WBG) power transistors, represented by silicon carbide (SiC) and gallium nitride (GaN) devices with superior figures of merits, opens the door for faster and more efficient power systems. To exploit the benefits of WBG devices, researchers need to evaluate the reliability and robustness of these devices comprehensively. The work presented here provides a study on the robustness of one mainstream GaN power transistor – the cascode GaN high-electron-mobility transistor (HEMT). This robustness test replicates the surge events in power electronics systems and exams their impact on power devices. Over the years, people have thoroughly investigated the surge-energy robustness of Si MOSFETs and concluded that Si MOSFETs are very robust against these surge events thanks to the avalanche mechanism. However, GaN HEMTs lack p-n junction structures between the two major electrodes, leading to the lack of avalanche ability. Instead, GaN HEMTs rely on the overvoltage capability to sustain the surge energy. For the first time, this work evaluates the surge-energy and overvoltage ruggedness of cascode GaN HEMTs, a major player in the GaN power device market. By analyzing the device failure mechanism and degradation behaviors, this research work provides insight into the weakness of these devices for both device designers and application engineers.

[pt] Bloqueio total de linhas submarinas de produção de petróleo devido ao depósito de parafina é um problema relevante para a indústria. Esse problema tem levado a perdas significativas associadas à diminuição de produção e à substituição de linhas obstruídas. O presente trabalho é um estudo sobre a viabilidade técnica de um procedimento para remoção de bloqueios ocasionados por depósitos de parafina. Nesse procedimento, a seção da linha de petróleo obstruída com parafina é aquecida por indução utilizando-se uma bobina externa posicionada sobre a linha no fundo do mar. O objetivo do trabalho é estimar o nível de potência elétrica necessária para amolecer a obstrução de parafina dentro da linha. Com esta finalidade, foi empregado um modelo numérico para simular o processo de condução de calor transiente para prever a distribuição de temperatura na parede da linha e na parafina sólida. Essa informação foi usada para estimar as dimensões básicas da seção da bobina de aquecimento e isolamento térmico empregado para minimizar as perdas de calor para o ambiente gelado da água do mar. Um estudo experimental de laboratório com uma seção de um duto submarino bloqueado com parafina foi conduzido para verificar as previsões do modelo numérico e para testar o desempenho da bobina de indução de aquecimento. Os resultados mostraram que as soluções numéricas obtidas apresentaram boa concordância com o experimento. Ainda, foi observado que os níveis de temperatura necessários para produzir o amolecimento da parafina na região bloqueada somente serão obtidos se toda a extensão da região bloqueada for aquecida pela ferramenta de indução. / [en] Total blockage of subsea petroleum production lines due to wax deposition is a relevant problem for the industry. This problem has led to significant capital losses associated with the loss of production and the substitution of plugged lines. The present work is a study of the feasibility of a remediation procedure aimed at helping the removal of wax plugs. In this procedure, the section of the oil line plugged with wax is inductively heated by means of an external coil positioned over the line at sea bed.The objective of the work is to estimate the level of electrical power required to soften the wax plug inside the line. To this end, a transient heat conduction model was employed to predict the temperature distribution in the line wall and solid wax. This information was employed to estimate the basic dimensions of the heating coil section and thermal insulation employed to minimize the heating losses to the cold sea water environment. A laboratory experimental study with a subsea pipeline section plugged with wax was conducted to verify the numerical model predictions and to test the performance of the inductive heating coil.The results showed that the numeric solutions obtained presented good agreement with the experiments. It was also observed that the necessary temperature levels to produce the paraffin softening in the blocked region will only be attained if the whole extension of the blocked region is heated by the induction tool.

The electrodeless plasma discharge is typically driven by radio frequency (RF) power supply within the range (0.2 &iexcl / 40 MHz). The applied power is coupled into the plasma inductively called inductively coupled plasma (ICP). RF ICP technique has achieved significance importance in a diversity of research and industrial applications for over the last threes decades. It is still required to undertake both theoretical and experimental research. In this work, RF ICP technique is applied on the torch modeling in 2D. Based on extended electromagnetic vector potential representation, an axisymmetric model in 2D is proposed for the calculations of the electromagnetic fields in an RF ICP torch. The influence of axial vector potential is included to the vector potential formulations. This is achieved by imposing a helical current carrying wire configuration. The corresponding governing equations are solved numerically by applying finite element method (FEM) using commercial partial differential equation solver (Flex PDE3). Based on this model, the plasma behavior and properties are examined in terms of plasma parameters. Besides, a comparative iii analysis is made between proposed model called helical configuration and the one currently available in the literature called circular configuration. This study shows relatively little difference between temperature fields predicted by two models. However, significant difference is observed between corresponding flows and electromagnetic fields. Especially, tangential flow which is observed in helical configuration vanishes in circular configuration. The proposed model offers an effective means of accounting for the variations of the helical coil geometry on the flow and temperature fields and achieving a better representation of the electromagnetic fields in the discharge. Finally, it is concluded that minimum number of turns (n = 2) yields significant difference between two models whereas, maximum allowable number of turns yield no distinctions on the results of two models in terms of azimuthally applied current. However, axial effect of current still exists but very small with respect to the result obtained with minimum number of turns.