• Refine Query
  • Source
  • Publication year
  • to
  • Language
  • 207
  • 114
  • Tagged with
  • 317
  • 317
  • 317
  • 317
  • 317
  • 30
  • 22
  • 22
  • 20
  • 20
  • 19
  • 19
  • 19
  • 18
  • 18
  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
21

The Road towards Integrated Micro-Supercapacitor: From 2D to 3D Device Geometries

Li, Fei 14 June 2021 (has links)
The rapid development of microelectronics has equally rapidly increased the demand for miniaturized energy storage devices. On-chip micro-supercapacitors (MSCs), as promising power candidates, possess great potential to complement or replace electrolytic capacitors (ECs) and microbatteries (MBs) in various applications. Recently, planar two-dimensional (2D) MSCs, composed of isolated thin-film microelectrodes with extremely short ionic diffusion path and free of separator on a single substrate, have become particularly attractive because they can be directly integrated with microelectronic devices on the same side of a flexible substrate to act as a standalone microsized power source. However, the areal capacities and energy densities of the 2D MSCs are commonly limited by the low voltage window and the thin layer of the electrode materials. Obviously, integrating more active material into cleverly designed three-dimensional (3D) electrode architectures will effectively increase the areal performance within a limited footprint area in spite of some loss of flexibility and cycling stability. However, it is still a big challenge to effciently and cost-effectively fabricate on-chip MSCs with high electro-chemical performance and abundant electrode structures. Here, three types of MSCs including graphene-based 2D planar MSCs, on-chip 3D interdigital MSCs and self-assembled 3D tubular MSCs were fabricated, respectively. The fabrication process, electrode materials structure and morphology, electrochemical performance, mechanical properties, integration process and difficulty, and practical application of these 2D and 3D devices are studied in detail.
22

Blitzschutz bei Biogasanlagen: Untersuchung zur Optimierung des Blitzschutzes bei Biogasanlagen

Kern, Alexander 30 October 2017 (has links)
Blitzschutz ist für Biogasanlagen entscheidend. Der Bericht wertet Blitzeinschläge/Blitzschäden in Biogasanlagen aus. Für Blitzschutz landwirtschaftlicher Biogasanlagen werden der Stand der Technik und Verbesserungsvorschläge dargestellt. Wichtige Erkenntnisse sind, dass das Beiblatt 2 zur DIN EN 62305-3 (VDE 0185-305-3) Stand der Sicherheitstechnik ist und für den Einzelfall eine Risikoanalyse nach DIN EN 62305-2 (VDE 0185-305-2) durchgeführt werden kann. Immer ist bei Biogasanlagen ein Blitzschutz-Potenzialausgleich für alle eingeführten Versorgungsleitungen und der koordinierte Überspannungsschutz für elektrische Leitungen der automatischen Brandschutzmaßnahmen erforderlich.
23

Design of an Ultra-wideband Radio Frequency Identification System with Chipless Transponders

Barahona Medina, Marvin Renan 17 September 2019 (has links)
The state-of-the-art commercially available radio-frequency identification (RFID) transponders are usually composed of an antenna and an application specific integrated circuit chip, which still makes them very costly compared to the well-established barcode technology. Therefore, a novel low-cost RFID system solution based on passive chipless RFID transponders manufactured using conductive strips on flexible substrates is proposed in this work. The chipless RFID transponders follow a specific structure design, which aim is to modify the shape of the impinged electromagnetic wave to embed anidentification code in it and then backscatter the encoded signal to the reader. This dissertation comprises a multidisciplinary research encompassing the design of low-cost chipless RFID transponders with a novel frequency coding technique, unlike usually disregarded in literature, this approach considers the communication channel effects and assigns a unique frequency response to each transponder. Hence, the identification codes are different enough, to reduce the detection error and improve their automatic recognition by the reader while working under normal conditions. The chipless RFID transponders are manufactured using different materials and state-of-the-art mass production fabrication processes, like printed electronics. Moreover, two different reader front-ends working in the ultra-wideband (UWB) frequency range are used to interrogate the chipless RFID transponders. The first one is built using high-performance off-theshelf components following the stepped frequency modulation (SFM) radar principle, and the second one is a commercially available impulse radio (IR) radar. Finally, the two readers are programmed with algorithms based on the conventional minimum distance and maximum likelihood detection techniques, considering the whole transponder radio frequency (RF) response, instead of following the commonly used approach of focusing on specific parts of the spectrum to detect dips or peaks. The programmed readers automatically identify when a chipless RFID transponder is placed within their interrogation zones and proceed to the successful recognition of its embedded identification code. Accomplishing in this way, two novel fully automatic SFM- and IRRFID readers for chipless transponders. The SFM-RFID system is capable to successfully decode up to eight different chipless RFID transponders placed sequentially at a maximum reading range of 36 cm. The IR-RFID system up to four sequentially and two simultaneously placed different chipless RFID transponders within a 50 cm range.:Acknowledgments Abstract Kurzfassung Table of Contents Index of Figures Index of Tables Index of Abbreviations Index of Symbols 1 Introduction 1.1 Motivation 1.2 Scope of Application 1.3 Objectives and Structure Fundamentals of the RFID Technology 2.1 Automatic Identification Systems Background 2.1.1 Barcode Technology 2.1.2 Optical Character Recognition 2.1.3 Biometric Procedures 2.1.4 Smart Cards 2.1.5 RFID Systems 2.2 RFID System Principle 2.2.1 RFID Features 2.3 RFID with Chipless Transponders 2.3.1 Time Domain Encoding 2.3.2 Frequency Domain Encoding 2.4 Summary Manufacturing Technologies 3.1 Organic and Printed Electronics 3.1.1 Substrates 3.1.2 Organic Inks 3.1.3 Screen Printing 3.1.4 Flexography 3.2 The Printing Process 3.3 A Fabrication Alternative with Aluminum or Copper Strips 3.4 Fabrication Technologies for Chipless RFID Transponders 3.5 Summary UWB Chipless RFID Transponder Design 4.1 Scattering Theory 4.1.1 Radar Cross-Section Definition 4.1.2 Radar Absorbing Material’s Principle 4.1.3 Dielectric Multilayers Wave Matrix Analysis 4.1.4 Frequency Selective Surfaces 4.2 Double-Dipoles UWB Chipless RFID Transponder 4.2.1 An Infinite Double-Dipole Array 4.2.2 Double-Dipoles UWB Chipless Transponder Design 4.2.3 Prototype Fabrication 4.3 UWB Chipless RFID Transponder with Concentric Circles 4.3.1 Concentric Circles UWB Chipless Transponder 4.3.2 Concentric Rings UWB Chipless RFID Transponder 4.4 Concentric Octagons UWB Chipless Transponders 4.4.1 Concentric Octagons UWB Chipless Transponder Design 1 4.4.2 Concentric Octagons UWB Chipless Transponder Design 2 4.5 Summary 5. RFID Readers for Chipless Transponders 5.1 Background 5.1.1 The Radar Range Equation 5.1.2 Range Resolution 5.1.3 Frequency Band Selection 5.2 Frequency Domain Reader Test System 5.2.1 Stepped Frequency Waveforms 5.2.2 Reader Architecture 5.2.3 Test System Results 5.3 Time Domain Reader 5.3.1 Novelda Radar 5.3.2 Test System Results 5.4 Summary Detection of UWB Chipless RFID Transponders 6.1 Background 6.2 The Communication Channel 6.2.1 AWGN Channel Modeling and Detection 6.2.2 Free-Space Path Loss Modeling and Normalization 6.3 Detection and Decoding of Chipless RFID Transponders 6.3.1 Minimum Distance Detector 6.3.2 Maximum Likelihood Detector 6.3.3 Correlator Detector 6.3.4 Test Results 6.4 Simultaneous Detection of Multiple UWB Chipless Transponders 6.5 Summary System Implementation 7.1 SFM-UWB RFID System with CR-Chipless Transponders 7.2 IR-UWB RFID System with COD1-Chipless Transponders 7.3 Summary Conclusion and Outlook References Publications Appendix A RCS Calculation Measurement Setups Appendix B Resistance and Skin Depth Calculation Appendix C List of Videos Test Videos Consortium Videos Curriculum Vitae
24

Multiterminal Source-Channel Coding

Wolf, Albrecht 26 September 2019 (has links)
Cooperative communication is seen as a key concept to achieve ultra-reliable communication in upcoming fifth-generation mobile networks (5G). A promising cooperative communication concept is multiterminal source-channel coding, which attracted recent attention in the research community. This thesis lays theoretical foundations for understanding the performance of multiterminal source-channel codes in a vast variety of cooperative communication networks. To this end, we decouple the multiterminal source-channel code into a multiterminal source code and multiple point-to-point channel codes. This way, we are able to adjust the multiterminal source code to any cooperative communication network without modification of the channel codes. We analyse the performance in terms of the outage probability in two steps: at first, we evaluate the instantaneous performance of the multiterminal source-channel codes for fixed channel realizations; and secondly, we average the instantaneous performance over the fading process. Based on the performance analysis, we evaluate the performance of multiterminal source-channel codes in three cooperative communication networks, namely relay, wireless sensor, and multi-connectivity networks. For all three networks, we identify the corresponding multiterminal source code and analyse its performance by the rate region for binary memoryless sources. Based on the rate region, we derive the outage probability for additive white Gaussian noise channels with quasi-static Rayleigh fading. We find results for the exact outage probability in integral form and closed-form solutions for the asymptotic outage probability at high signal-to-noise ratio. The importance of our results is fourfold: (i) we give the ultimate performance limits of the cooperative communication networks under investigation; (ii) the optimality of practical schemes can be evaluated with respect to our results, (iii) our results are suitable for link-level abstraction which reduces complexity in network-level simulation; and (iv) our results demonstrate that all three cooperative communication networks are key technologies to enable 5G applications, such as device to device and machine to machine communications, internet of things, and internet of vehicles. In addition, we evaluate the performance improvement of multiterminal source-channel codes over other (non-)cooperative communications concepts in terms of the transmit power reduction given a certain outage probability level. Moreover, we compare our theoretical results to simulated frame-error-rates of practical coding schemes. Our results manifest the superiority of multiterminal source-channel codes over other (non-)cooperative communications concepts.
25

Materials for DRAM Memory Cell Applications

Schroeder, Uwe, Cho, Kyuho, Slesazeck, Stefan 06 May 2022 (has links)
Semiconductor memory is one of the key technologies driving the success of Si-based information technology within the last five decades. The most prominent representative memory type, the dynamic random access memory(DRAM)was patented in 1967 and was introduced into the market by Intel Corporation in 1972. Until the year 2001 and the realization of the 110 nm technology node, DRAM was the driving force on the lithography shrink roadmap, before NAND FLASH took over that role. Hence, the development of the DRAM technology was long time the forerunner for the exponentially growing large-scale integration and promoted similar advances in logic chips. One of the reasons of the success of the DRAM is its simple cell structure, which consists of only one transistor (1T) and one capacitor (1C), where the information is stored in form of a charge.
26

Integrated Distributed Amplifiers for Ultra-Wideband BiCMOS Receivers Operating at Millimeter-Wave Frequencies

Testa, Paolo Valerio 30 November 2018 (has links)
Millimetre-wave technology is used for applications such as telecommunications and imaging. For both applications, the bandwidth of existing systems has to be increased to support higher data rates and finer imaging resolutions. Millimetrewave circuits with very large bandwidths are developed in this thesis. The focus is put on amplifiers and the on-chip integration of the amplifiers with antennas. Circuit prototypes, fabricated in a commercially available 130nm Silicon-Germanium (SiGe) Bipolar Complementary Metal-Oxide-Semiconductor (BiCMOS) process, validated the developed techniques. Cutting-edge performances have been achieved in the field of distributed and resonant-matched amplifiers, as well as in that of the antenna-amplifier co-integration. Examples are as follows: - A novel cascode gain-cell with three transistors was conceived. By means of transconductance peaking towards high frequencies, the losses of the synthetic line can be compensated up to higher frequencies. The properties were analytically derived and explained. Experimental demonstration validated the technique by a Traveling-Wave Amplifier (TWA) able to produce 10 dB of gain over a frequency band of 170GHz.# - Two Cascaded Single-Stage Distributed Amplifiers (CSSDAs) have been demonstrated. The first CSSDA, optimized for low power consumption, requires less than 20mW to provide 10 dB of gain over a frequency band of 130 GHz. The second amplifier was designed for high-frequency operation and works up to 250 GHz leading to a record bandwidth for distributed amplifiers in SiGe technology. - The first complete CSSDA circuit analysis as function of all key parameters was presented. The typical degradation of the CSSDA output matching towards high frequencies was analytically quantified. A balanced architecture was then introduced to retain the frequency-response advantages of CSSDAs and yet ensure matching over the frequency band of interested. A circuit prototype validated experimentally the technique. - The first traveling-wave power combiner and divider capable of operation from the MHz range up to 200 GHz were demonstrated. The circuits improved the state of the art of the maximum frequency of operation and the bandwidth by a factor of five. - A resonant-matched balanced amplifier was demonstrated with a centre frequency of 185 GHz, 10 dB of gain and a 55GHz wide –3 dB-bandwidth. The power consumption of the amplifier is 16.8mW, one of the lowest for this circuit class, while the bandwidth is the broadest reported in literature for resonant-matched amplifiers in SiGe technology.
27

Millimeter Wave Line-of-Sight Spatial Multiplexing: Antenna Topology and Signal Processing

Song, Xiaohang 15 February 2019 (has links)
Fixed wireless communication is a cost-efficient solution for flexible and rapid front-/backhaul deployments. Technologies including dual polarization, carrier aggregation, and higher order modulation schemes have been developed for enhancing its throughput. In order to better support the massive traffic increment during network evolution, novel wireless backhaul solutions with possible new dimensions in increasing the spectral efficiency are needed. Line-of-Sight (LoS) Multiple-Input-Multiple-Output (MIMO) communication is such a promising candidate allowing the throughput to scale linearly with the deployed antenna pairs. Spatial multiplexing with sub-channels having approximately equal quality exists within a single LoS direction. In addition, operating at millimeter wave (mmWave) frequencies or higher, the abundantly available bandwidth can further enhance the throughput of LoS MIMO communication. The mmWave LoS MIMO communication in this work exploits the spatial multiplexing from the structured phase couplings of a single path direction, while most of the state-of-the-art works in mmWave communication focus on the spatial multiplexing from the spatial signature of multiple path directions. Challenges: The performance of a LoS MIMO system is highly dependent on the antenna topology. Topologies resulting in theoretically orthogonal channels are considered as optimal arrangements. The general topology solution from a unified viewpoint is unknown. The known optimal arrangements in the literature are rather independently derived and contain restrictions on their array planes. Moreover, operating at mmWave frequencies with wideband signals introduces additional challenges. On one hand, high pathloss is one limiting factor of the received signal power. On the other hand, high symbol rates and relatively high antenna numbers create challenges in signal processing, especially the required complexity for compensating hardware imperfections and applying beamforming. Targets: In this thesis, we focus on antenna topologies and signal processing schemes to effectively handle the complexity challenge in LoS MIMO communications. Considering the antenna topology, we target a general solution of optimal arrangements on any arbitrarily curved surface. Moreover, we study the antenna topologies with which the system gains more streams and better received signals. Considering the signal processing, we look for low complexity schemes that can effectively compensate the hardware impairments and can cope with a large number of antennas. Main Contributions: The following models and algorithms are developed for understanding mmWave LoS spatial multiplexing and turning it into practice. First, after analyzing the relation between the phase couplings and the antenna positions in three dimensional space, we derive a channel factorization model for LoS MIMO communication. Based on this, we provide a general topology solution from a projection point of view and show that the resulting spatial multiplexing is robust against moderate displacement errors. In addition, we propose a multi-subarray LoS MIMO system for jointly harvesting the spatial multiplexing and array gains. Then, we propose a novel algorithm for LoS MIMO channel equalization, which is carried out in the reverse order w.r.t. the channel factorization model. The number of multiplications in both digital and analog implementations of the proposed solution is found to increase approximately linearly w.r.t. the number of antennas. The proposed algorithm thus potentially reduces complexity for equalizing the channel during the system expansion with more streams. After this, we focus on algorithms that can effectively estimate and compensate the hardware impairments. A systolic/pipelined processing architecture is proposed in this work to achieve a balance between computational complexity and performance. The proposed architecture is a viable approach that scales well with the number of MIMO streams. With the recorded data from a hardware-in-the-loop demonstrator, it is shown that the proposed algorithms can provide reliable signal estimates at a relatively low complexity level. Finally, a channel model is derived for mmWave systems with multiple widely spaced subarrays and multiple paths. The spatial multiplexing gain from the spatial signature of multiple path directions and the spatial multiplexing gain from the structured phase couplings of a single path direction are found simultaneously at two different levels of the antenna arrangements. Attempting to exploit them jointly, we propose to use an advanced hybrid analog/digital beamforming architecture to efficiently process the signals at reasonable costs and complexity. The proposed system can overcome the low rank property caused by the limited number of propagation paths.
28

A 30 Gb/s High-Swing, Open-Collector Modulator Driver in 250 nm SiGe BiCMOS

Giuglea, Alexandru, Belfiore, Guido, Khafaji, Mahdi, Henker, Ronny, Ellinger, Frank 24 April 2019 (has links)
This paper presents a modulator driver realized as a breakdown voltage doubler which can provide a high output swing of 7.6 Vpp,diff for load impedances as low as 30 Ω, thus overcoming the limitation imposed by the collector-emitter breakdown voltage. The open-collector design gives an important degree of freedom regarding the modulator load to be driven, while significantly reducing the circuit's power consumption. The driver is capable of running at 30 Gb/s while dissipating 1 W of DC power. Thanks to the inductorless design, the active area occupied by the circuit is only 0.28 mm × 0.23 mm. The driver was realized in a 250 nm SiGe BiCMOS technology.
29

Beschleunigerarchitekturen zur energieeffizienten Datenbank-Anfrageverarbeitung in Mehrprozessorsystemen

Haas, Sebastian 21 May 2019 (has links)
Die Datenverarbeitung auf einer weltweit stetig wachsenden Informationsmenge und die hohen Anforderungen an die Energieeffizienz der Rechensysteme sind allgegenwärtige Herausforderungen der heutigen Zeit. Dabei werden zunehmend Datenbanken und deren Funktionalitäten eingesetzt, um diese großen Datenmengen effizient zu verwalten, abzuspeichern und zu verarbeiten. Auf Grund ihrer universellen Anwendbarkeit und der hohen Leistungsfähigkeit werden zumeist hoch-performante General-Purpose (GP) Prozessoren für administrative als auch für die Anfrageverarbeitung in Datenbanksystemen eingesetzt. Die Anfrageverarbeitung führt dabei eine Reihe von Operatoren wie z. B. das Suchen, Sortieren, oder Hashing aus, die signifikant die Gesamtleistung des Datenbanksystems beeinflussen. Um die weiter steigenden Anforderungen an Durchsatz, Latenz und Verlustleistung zu erfüllen, wurden bisher die Taktfrequenzen und damit die Leistungsfähigkeit von GP-Prozessoren kontinuierlich erhöht. In Zukunft werden jedoch die physikalischen Eigenschaften der verwendeten Halbleitermaterialien die Rechenleistung begrenzen. Diese Arbeit entwickelt und analysiert Beschleunigerarchitekturen für die Datenbank-Anfrageverarbeitung, um die Leistungsfähigkeit der zugrundeliegenden Datenbankoperatoren zu steigern. Die Datenbankbeschleuniger (DBA) werden als anwendungsspezifische Hardwareblöcke (ASIC) und als Prozessor mit erweiterten Befehlssatz (ASIP) implementiert, die eine Parallelisierung der Algorithmen auf Bit-, Daten- und Befehlsebene ermöglichen. Der erste Ansatz erlaubt eine hohe Beschleunigung bei gleichzeitig niedrigem Flächen- und Leistungsverbrauch der Hardware. Im Gegensatz dazu steht beim ASIP-Ansatz bereits ein konfigurierbarer Basisprozessor zur Verfügung, der die Befehlssteuerung übernimmt und damit eine einfache Anpassung des DBAs an zahlreiche Datenbankoperatoren ermöglicht. Die vorgestellten DBAs erreichen damit die Leistungsfähigkeit von optimierten GP-Prozessoren bei einer um bis zu drei Größenordnungen höheren Energie- und Flächeneffizienz. Für die Parallelisierung der Datenbankoperatoren auf Taskebene werden die DBAs in das Tomahawk Multiprozessorsystem auf einem Chip (MPSoC) integriert, das ein skalierbares Network-on-Chip und DMA-Controller für einen intelligenten Datentransfer bereitstellt. Eine zentrale Scheduling-Einheit arbeitet dabei den Anfrageausführungsplan ab und steuert die Zuweisung der Tasks auf die Verarbeitungseinheiten und den Transfer der Daten zu einem externen Speicher. Des Weiteren ist die Skalierung von Taktfrequenzen und Versorgungsspannungen möglich, um Durchsatz und Leistungsverbrauch an die Lastanforderungen anzupassen und damit den Energieverbrauch zu minimieren. Darüber hinaus wird das Tomahawk MPSoC mit Hilfe von Simulationen in einem virtuellen Prototyp und mit analytischen Modellen der Datenbankoperatoren hinsichtlich der Skalierbarkeit untersucht. Diese Auswertungen zeigen das Verhalten der Algorithmen bei steigender Prozessoranzahl und wachsenden Kardinalitäten sowie in Abhängigkeit der Speicherbandbreiten und relevanter algorithmusspezifischer Parameter.
30

On Fault Resilient Network-on-Chip for Many Core Systems

Moriam, Sadia 24 May 2019 (has links)
Rapid scaling of transistor gate sizes has increased the density of on-chip integration and paved the way for heterogeneous many-core systems-on-chip, significantly improving the speed of on-chip processing. The design of the interconnection network of these complex systems is a challenging one and the network-on-chip (NoC) is now the accepted scalable and bandwidth efficient interconnect for multi-processor systems on-chip (MPSoCs). However, the performance enhancements of technology scaling come at the cost of reliability as on-chip components particularly the network-on-chip become increasingly prone to faults. In this thesis, we focus on approaches to deal with the errors caused by such faults. The results of these approaches are obtained not only via time-consuming cycle-accurate simulations but also by analytical approaches, allowing for faster and accurate evaluations, especially for larger networks. Redundancy is the general approach to deal with faults, the mode of which varies according to the type of fault. For the NoC, there exists a classification of faults into transient, intermittent and permanent faults. Transient faults appear randomly for a few cycles and may be caused by the radiation of particles. Intermittent faults are similar to transient faults, however, differing in the fact that they occur repeatedly at the same location, eventually leading to a permanent fault. Permanent faults by definition are caused by wires and transistors being permanently short or open. Generally, spatial redundancy or the use of redundant components is used for dealing with permanent faults. Temporal redundancy deals with failures by re-execution or by retransmission of data while information redundancy adds redundant information to the data packets allowing for error detection and correction. Temporal and information redundancy methods are useful when dealing with transient and intermittent faults. In this dissertation, we begin with permanent faults in NoC in the form of faulty links and routers. Our approach for spatial redundancy adds redundant links in the diagonal direction to the standard rectangular mesh topology resulting in the hexagonal and octagonal NoCs. In addition to redundant links, adaptive routing must be used to bypass faulty components. We develop novel fault-tolerant deadlock-free adaptive routing algorithms for these topologies based on the turn model without the use of virtual channels. Our results show that the hexagonal and octagonal NoCs can tolerate all 2-router and 3-router faults, respectively, while the mesh has been shown to tolerate all 1-router faults. To simplify the restricted-turn selection process for achieving deadlock freedom, we devised an approach based on the channel dependency matrix instead of the state-of-the-art Duato's method of observing the channel dependency graph for cycles. The approach is general and can be used for the turn selection process for any regular topology. We further use algebraic manipulations of the channel dependency matrix to analytically assess the fault resilience of the adaptive routing algorithms when affected by permanent faults. We present and validate this method for the 2D mesh and hexagonal NoC topologies achieving very high accuracy with a maximum error of 1%. The approach is very general and allows for faster evaluations as compared to the generally used cycle-accurate simulations. In comparison, existing works usually assume a limited number of faults to be able to analytically assess the network reliability. We apply the approach to evaluate the fault resilience of larger NoCs demonstrating the usefulness of the approach especially compared to cycle-accurate simulations. Finally, we concentrate on temporal and information redundancy techniques to deal with transient and intermittent faults in the router resulting in the dropping and hence loss of packets. Temporal redundancy is applied in the form of ARQ and retransmission of lost packets. Information redundancy is applied by the generation and transmission of redundant linear combinations of packets known as random linear network coding. We develop an analytic model for flexible evaluation of these approaches to determine the network performance parameters such as residual error rates and increased network load. The analytic model allows to evaluate larger NoCs and different topologies and to investigate the advantage of network coding compared to uncoded transmissions. We further extend the work with a small insight to the problem of secure communication over the NoC. Assuming large heterogeneous MPSoCs with components from third parties, the communication is subject to active attacks in the form of packet modification and drops in the NoC routers. Devising approaches to resolve these issues, we again formulate analytic models for their flexible and accurate evaluations, with a maximum estimation error of 7%.

Page generated in 0.1874 seconds