Cabrera Guerrero, Juan Alberto
04 July 2022
Communication systems are experiencing a fundamental change. There are novel applications that require an increased performance not only of throughput but also latency, reliability, security, and heterogeneity support from these systems. To fulfil the requirements, future systems understand communication not only as the transport of bits but also as their storage, processing, and relation. In these systems, every network node has transport storage and computing resources that the network operator and its users can exploit through virtualisation and softwarisation of the resources. It is within this context that this work presents its results. We proposed distributed coded approaches to improve communication systems. Our results improve the reliability and latency performance of the transport of information. They also increase the reliability, flexibility, and throughput of storage applications. Furthermore, based on the lessons that coded approaches improve the transport and storage performance of communication systems, we propose a distributed coded approach for the computing of novel in-network applications such as the steering and control of cyber-physical systems. Our proposed approach can increase the reliability and latency performance of distributed in-network computing in the presence of errors, erasures, and attackers.
25 September 2023
The scope of this work is the development of a 60 GHz flexible transceiver frontend by adopting an economic prototyping approach. Such a platform can validate the proposed protocols for the 60 GHz band in a real wireless environment, especially the physical layer security concept. The development course uses the hybrid architecture with off-the-shelf components and custom-designed RF chain blocks on printed circuit technology. Challenge in this approach is the coarse resolution of the selected manufacturing technology and higher process tolerance. This work extends the state-of-the-art by proposing etching-resilient RF chain blocks on wide bandwidths. It presents the design validation of each block and performance analysis for various manufacturing conditions. The study also reviews and proposes a high-frequency interconnect model for bondwires, vital in a frontend design. Parasitics' compensation of the interconnects at millimeter-wave operation is proposed, compatible with printed circuit technology. The 60 GHz frontend is realized by packaging the designed RF blocks and off-the-shelf components with optimized and characterized high-frequency interconnects. The frontend, equipped with a tailor-made antenna duplexer, is reconfigurable for frequency, power, and modulation scheme. The developed frontend is characterized for local oscillator, transmitter, and receiver operations. The adaptability of the frontend allows it to be used as an agent in a heterogeneous network. Two units of the developed frontends are used in a network for frequency domain channel sounding. The antenna duplexer ensures channel reciprocity in bidirectional sounding campaigns. Matched two-way channel response is achieved in various indoor environments, which endorses the frontend for channel reciprocity key generation. Finally, the frontend units are successfully deployed in a physical layer security demonstrator.:Abstract Chapter1: Introduction Chapter 2: Fundamentals and state-of-the-art Chapter 3: The design Chapter 4: Integration and characterization Chapter 5: Application example: Channel sounder Chapter 6: Summary and future work Appendices Bibliography
Through Silicon Via Field-Effect Transistor with Hafnia-based Ferroelectrics and the Doping of Silicon by Gallium Implantation Utilizing a Focused Ion Beam SystemWinkler, Felix 26 November 2020 (has links)
3-dimensional integration has become a standard to further increase the transistor density and to enhance the integrated functionality in microchips. Integrated circuits are stacked on top of each other and copper-filled through-silicon VIAs (TSVs) are the industry-accepted choice for their vertical electrical connection. The aim of this work is to functionalize the TSVs by implementing vertical field-effect transistors inside the via holes. The front and back sides of 200 ... 300 µm thin silicon wafers were doped to create the source/drain regions of n- and p-FETs. The TSVFETs showed very stable saturation currents and on/off current ratios of about 10^6 (n-TSVFET) and 10^3 (p-TSVFET) for a gate voltage magnitude of 4V. The use of hafnium zirconium oxide on a thin SiO_2 interface layer as gate dielectric material in a p-TSVFET, enabled the implementation of a charge trapping memory inside the TSVs, showing a memory window of about 1V. This allows the non-volatile storage of the transistor on/off state. In addition, the demonstration of the use of gallium as the source/drain dopant in planar p-FET test structures (ion implanted from a focused ion beam tool) paves the way for maskless doping and for a process flow with a low thermal budget. It was shown, that ion implanted gallium can be activated and annealed at relatively low temperatures of 500 °C ... 700 °C.:Abstract / Kurzzusammenfassung Danksagung Index I List of Figures III List of Tables X List of Symbols XI List of Abbreviations XV 1 Introduction 1 2 Fundamentals 5 2.1 Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) 5 2.1.1 Historical Development - Technological Advancements 7 2.1.2 Field-Effect Transistors in Semiconductor Memories 10 2.2 3D Integration and the Use of TSVs (Through Silicon VIAs) 16 2.3 Doping of Silicon 19 2.3.1 Doping by Thermal Diffusion 20 2.3.2 Doping by Ion Implantation 22 3 Electrical Characterization 24 3.1 Resistivity Measurements 24 3.1.1 Resistance Determination by Four-Point Probes Measurement 24 3.1.2 Contact Resistivity 27 3.1.3 Doping Concentration 32 3.2 C-V Measurements 35 3.2.1 Fundamentals of MIS C-V Measurements 35 3.2.2 Interpretation of C-V Measurements 37 3.3 Transistor Measurements 41 3.3.1 Output Characteristics (I_D-V_D) 41 3.3.2 Transfer Characteristics (I_D-V_G) 42 4 TSV Transistor 45 4.1 Idea and Motivation 45 4.2 Design and Layout of the TSV Transistor 47 4.2.1 Design of the TSV Transistor Structures 47 4.2.2 Test Structures for Planar FETs 48 5 Variations in the Integration Scheme of the TSV Transistor 51 5.1 Doping by Diffusion from Thin Films 51 5.1.1 Determination of Doping Profiles 52 5.1.2 n- and p- TSVFETs Doped Manufactures by the Use of the Diffusion Technique 59 5.2 Ferroelectric Hafnium-Zirconium-Oxide (HZO) in the Gate Stack 81 5.2.1 Planar ferroelectric p-MOSFETs Doped by Thermal Diffusion 82 5.2.2 p-TSVFETs with Hafnium-Zirconium-Oxide Metal Gate 90 5.3 Doping by Ion Implantation of Gallium with a Focused Ion Beam (FIB) Tool 96 5.3.1 Ga doped Si Diodes 97 5.3.2 Planar p-MOSFETs Doped by Ga Implantation 108 5.3.3 Proposal for a parallel integration of Cu TSVs and p-TSVFETs 117 6 Summary and Outlook 120 Bibliography XVIII A Appendix XXXVI A.1 Resistivity and Dopant Density XXXVI A.2 Mask set for the TSVFET XXXVII A.3 Mask Design of the Planar Test Structures XXXVIII Curriculum Vitae XXXIX List of Scientific Publications XLI
10 October 2023
Massenanpassung, kleine Losgrößen, hohe Variabilität der Produkttypen und ein sich während des Lebenszyklus einer industriellen Anlage änderndes Produktportfolio sind aktuelle Trends der Industrie. Durch eine zunehmende Entkopplung der Entwicklung von Software- und Hardwarekomponenten im industriellen Kontext, entstehen immer häufiger Kompatibilitätsprobleme innerhalb von industriellen Steuerungen. In dieser Arbeit wird mittels Literaturrecherche und angewandter Forschung ein Strategiekonzept zur Kompatibilitätsprüfung hergeleitet und diskutiert. Dieses vierphasige Konzept ermittelt Inkompatibilitäten zwischen Software- und Hardwarekomponenten im Umfeld von industriellen Steuerungen und ermöglicht Testingenieuren das frühzeitige Erkennen von Problemen. Durch eine automatische Durchführung der Kompatibilitätsprüfung auf einem externen Industrie PC kann die Kompatibilitätsprüfung sowohl beim Aufspielen neuer Software auf die industrielle Steuerung als auch beim Neustart der Steuerung ablaufen. Somit werden Änderungen an den Komponenten stetig erkannt und Inkompatibilitäten vermieden. Weiterhin kann durch die frühzeitige Erkennung sichergestellt werden, dass eine Anlage dauerhaft lauffähig bleibt. Anhand einer Diskussion werden Mittel festgestellt, um die Robustheit und Anwendbarkeit des vorgestellten Konzeptes zusätzlich zu festigen.:1 Motivation 1 1.1 Aufgabenanalyse 3 1.1.1 Forschungsfragen und Teilaufgaben 3 1.1.2 Aufgabenkomplexe 4 1.1.3 Eingrenzung der Aufgabenstellung 5 1.1.4 Ziel der Arbeit 6 1.1.5 Festsetzung von Formulierungen 6 2 Einführung und Stand der Technik 7 2.1 VIBN von industriellen Anlagen 7 2.1.1 Teststrategien aus der VIBN 9 126.96.36.199 Model-in-the-Loop 9 188.8.131.52 Software-in-the-Loop 9 184.108.40.206 Hardware-in-the-Loop 10 220.127.116.11 Konklusion und Forschungsbestrebungen 11 2.2 CS in industriellen Anlagen 12 2.2.1 Sicherheitsziel 13 2.2.2 Teststrategien aus der CS 13 18.104.22.168 Signaturbasierte Erkennung 14 22.214.171.124 Anomaliebasierte Erkennung 14 126.96.36.199 Konklusion und Forschungsbestrebungen 16 2.3 Interoperabilität als Kompatibilitätsmaß 16 2.4 Testautomatisierung und Test Case Generierung 17 2.5 Allgemeine Softwareteststrategien 17 2.5.1 Modellbasiertes Testen 17 2.5.2 Funktionale Tests 18 2.6 Allgemeine Hardware Teststrategien 19 2.6.1 Modellbasiertes Testen 19 2.6.2 Manuelles Testen 19 2.7 Interoperabilität in industriellen Anlagen 20 2.7.1 Definitionen der Interoperabilität 20 2.7.2 Herausforderungen der Interoperabilität 22 2.7.3 Implementierung von Interoperabilität 22 188.8.131.52 Syntaktische Interoperabilität 23 184.108.40.206 Semantische Interoperabilität 23 2.7.4 Vertikale Integration 24 2.7.5 Horizontale Integration 25 3 Anforderungsanalyse 27 3.1 Adaption von Strategien der VIBN und CS 27 3.2 Anforderungen 28 3.2.1 Anforderungen an die Kompatibilitätsprüfung 28 3.2.2 Anforderungen an die Hardwarekomponenten 29 3.2.3 Anforderungen an die Softwarekomponenten 29 4 Konzept 30 4.1 Komponenten des Teststrategiekonzeptes 30 4.1.1 SPS Selbsttest 32 4.1.2 Export & Import des Soll-Zustandes 32 4.1.3 Ermittlung des Ist-Zustandes 35 4.1.4 Vergleich des Soll- & Ist-Zustandes 35 4.2 Fehlerdetektionstabellen 36 4.3 Reaktionen auf Inkompatibilitäten 38 5 Evaluation 39 5.1 Methodik und Evaluationskriterien 39 5.2 Anwendungsbeispiel 39 5.3 Referenzsystem für Evaluation 41 5.4 Durchführung Evaluation 41 5.5 Erfüllung der Anforderungen an die Kompatibilitätsprüfung 46 6 Diskussion 48 6.1 Beantwortung der Forschungsfragen 48 6.2 Diskussion zur Forschungsmethodik 48 6.3 Bewertung des Konzeptes 49 7 Zusammenfassung und Ausblick 50 7.1 Zusammenfassung 50 7.2 Ausblick und weitere Forschungsarbeit 51 Literaturverzeichnis 52 / Mass customization, small batch sizes, high variability of product types and a changing product portfolio during the life cycle of an industrial plant are current trends in the industry. Due to an increasing decoupling of the development of software and hardware components in an industrial context, compatibility problems within industrial control systems arise more and more frequently. In this thesis, a strategy concept for compatibility testing is derived and discussed by means of literature review and applied research. This 4-phased strategy concept identifies incompatibilities between software and hardware components in the industrial control environment and enables test engineers to detect problems at an early stage. By automating the compatibility test on an external I-PC, the test can be run both when new software is installed on the industrial controller and when the controller is restarted. Thus, changes to the components are constantly detected and incompatibilities are avoided. Furthermore, early incompatibility detection can ensure that a system remains permanently operational. Based on a discussion, additionally strategies are identified to consolidate the robustness and applicability of the presented concept.:1 Motivation 1 1.1 Aufgabenanalyse 3 1.1.1 Forschungsfragen und Teilaufgaben 3 1.1.2 Aufgabenkomplexe 4 1.1.3 Eingrenzung der Aufgabenstellung 5 1.1.4 Ziel der Arbeit 6 1.1.5 Festsetzung von Formulierungen 6 2 Einführung und Stand der Technik 7 2.1 VIBN von industriellen Anlagen 7 2.1.1 Teststrategien aus der VIBN 9 220.127.116.11 Model-in-the-Loop 9 18.104.22.168 Software-in-the-Loop 9 22.214.171.124 Hardware-in-the-Loop 10 126.96.36.199 Konklusion und Forschungsbestrebungen 11 2.2 CS in industriellen Anlagen 12 2.2.1 Sicherheitsziel 13 2.2.2 Teststrategien aus der CS 13 188.8.131.52 Signaturbasierte Erkennung 14 184.108.40.206 Anomaliebasierte Erkennung 14 220.127.116.11 Konklusion und Forschungsbestrebungen 16 2.3 Interoperabilität als Kompatibilitätsmaß 16 2.4 Testautomatisierung und Test Case Generierung 17 2.5 Allgemeine Softwareteststrategien 17 2.5.1 Modellbasiertes Testen 17 2.5.2 Funktionale Tests 18 2.6 Allgemeine Hardware Teststrategien 19 2.6.1 Modellbasiertes Testen 19 2.6.2 Manuelles Testen 19 2.7 Interoperabilität in industriellen Anlagen 20 2.7.1 Definitionen der Interoperabilität 20 2.7.2 Herausforderungen der Interoperabilität 22 2.7.3 Implementierung von Interoperabilität 22 18.104.22.168 Syntaktische Interoperabilität 23 22.214.171.124 Semantische Interoperabilität 23 2.7.4 Vertikale Integration 24 2.7.5 Horizontale Integration 25 3 Anforderungsanalyse 27 3.1 Adaption von Strategien der VIBN und CS 27 3.2 Anforderungen 28 3.2.1 Anforderungen an die Kompatibilitätsprüfung 28 3.2.2 Anforderungen an die Hardwarekomponenten 29 3.2.3 Anforderungen an die Softwarekomponenten 29 4 Konzept 30 4.1 Komponenten des Teststrategiekonzeptes 30 4.1.1 SPS Selbsttest 32 4.1.2 Export & Import des Soll-Zustandes 32 4.1.3 Ermittlung des Ist-Zustandes 35 4.1.4 Vergleich des Soll- & Ist-Zustandes 35 4.2 Fehlerdetektionstabellen 36 4.3 Reaktionen auf Inkompatibilitäten 38 5 Evaluation 39 5.1 Methodik und Evaluationskriterien 39 5.2 Anwendungsbeispiel 39 5.3 Referenzsystem für Evaluation 41 5.4 Durchführung Evaluation 41 5.5 Erfüllung der Anforderungen an die Kompatibilitätsprüfung 46 6 Diskussion 48 6.1 Beantwortung der Forschungsfragen 48 6.2 Diskussion zur Forschungsmethodik 48 6.3 Bewertung des Konzeptes 49 7 Zusammenfassung und Ausblick 50 7.1 Zusammenfassung 50 7.2 Ausblick und weitere Forschungsarbeit 51 Literaturverzeichnis 52
23 December 2020
The realization of wireless ultra-reliable low-latency communications (URLLC) is one of the key challenges of the fifth generation (5G) of mobile communications systems and beyond. Ensuring ultra-high reliability together with a latency in the (sub-)millisecond range is expected to enable self-driving cars, wireless factory automation, and the Tactile Internet. In wireless communications, reliability is usually only considered as percentage of successful packet delivery, aiming for 1 − 10⁻⁵ up to 1 − 10⁻⁹ in URLLC.
14 September 2017
With the advancement of semiconductor technology, the System on Chip (SoC) is becoming more and more complex, so the on-chip communication has become a bottleneck of SoC Design. Since the traditional bus system is inefficient and not scalable, the Network-On-Chip (NoC) has emerged as the promising communication mechanism for complex SoCs. As some systems have specific performance requirements, such as a minimum throughput (for real-time streaming data) or bounded latency (for interrupts, process synchronization, etc), communication with Guaranteed Service (GS) support becomes crucial for predictable SoC architectures. Circuit Switching (CS) is a popular approach to support GS, which firstly has to allocate an exclusively connection (circuit) between the source and destination nodes, and then the data packets are delivered over this connection. However, it is inefficient and inflexible because the resource is occupied by single connection during its whole lifetime, which can block other communications. Hence, two extensions of CS have been proposed to share resources: i) Time-Division Multiplexing (TDM), in which the available link capacity is split into multiple time slots to be shared by different flows in TDM scheme; and ii) Space-Division-Multiplexing (SDM), in which only a subset (sub-channel) of the link wires is exclusively allocated to a specific connection, while the remaining wires of the link can be used by other flows. The connection allocation is critical for CS, since the data delivery can start only after the associated connection is allocated. In this thesis, we propose a dedicated hardware connection allocator to solve the dynamic connection allocation problem for CS NoCs, which has to i) allocate a contention-free path between source-destination pairs and ii) allocate appropriate portions of link bandwidth (appropriate number of time slots and subsets) along the path. The dedicated connection allocator, called NoCManager, solves the connection allocation problem by employing a trellis-search based shortest path algorithm. The trellis search can explore all possible paths between source node and destination. Moreover, it shall find the requested path in a fixed low latency and can guarantee the path optimality in terms of path length if the path is available. In this thesis, two different trellis graphs, Forward-Backtrack trellis and Register-Exchange trellis are proposed. The Forward-Backtrack trellis completes the path search in two steps: forward search and backtracking. Firstly, the forward search begins at source node that traverses the network to find the free path. When destination node is reached, the backtrack starts from destination to select the survivor path and collect the associated path parameters. However, Register-Exchange trellis saves the entire survivor path sequences during forward search. Consequently, the backtracking step can be omitted, and thus the allocation time is halved compared to forward-backtrack approaches. Moreover, each trellis graph consists of three categories, unfolded structure, folded structure and bidirectional structure. The unfolded structure can provide high allocation speed while folded structure is more efficient from a hardware point of view. The bidirectional structure starts the search at two sides, source node and destination node simultaneously, so the allocation speed is 2 times faster than previous unidirectional search. Furthermore, in order to address the scalability issue of previous centralized systems, the partitioned architecture (i.e. spatial partitioning technique) is proposed to divide the large system into multiple smaller differentiated logical partitions served by local NoCManagers. This partitioning technique keeps the request load of the manager and manager-node communication overhead moderate. Inside each partition, the path search problem is solved by a local manager with trellis-search algorithm. To establish a path that crosses partitions, the managers communicate with each other in distributed manner to converge the global path. In order to further enhance the path diversity and resource utilization, we adopt the combined TDM and SDM technique. In combined TDM-SDM approach, each SDM sub-channel is split into multiple time slots so that can be shared by multiple flows. Hence, the number of sub-channels can be kept moderate to reduce router complexity, while still providing higher path diversity than TDM scheme. In order to investigate and optimize TDM-SDM partitioning strategy, we studied the influence of different TDM-SDM link partitioning strategies on success rate and path length that allowed us to find the optimal solution. The dedicated connection allocator using the trellis-search algorithm is employed for TDM, SDM and TDM-SDM CS. In the end, we present the router architecture that combines the circuit-switching network (for GS communication) and packet-switching network (for best-effort communication).
09 November 2021
The monolithic integration of III-V semiconductors on Si substrates is a part of a long-term technological roadmap for the semiconductor industry towards More-than-Moore technologies. Despite of the different lattice constants and thermal expansion coefficients, research efforts over the last two decades have shown that III-V crystals with a high structural quality can be grown epitaxially in the form of nanowires directly on Si using CMOS-compatible (Au-free) methods. Among other III-V compounds, InxGa1-xAs is of the special interest for the use in infrared photonics and high-speed electronics due to its tunable direct bandgap and low electron effective mass, respectively. For comparison, InxGa1-xAs thin films are typically grown on lattice-matched InP substrates with a limited range of compositions at around x=0.52. The realization of InxGa1-xAs nanowires on Si, though, has been proved challenging owing to the limited In-content when the nanowires are grown Ga-catalyzed or the high density of stacking faults when the nanowires are grown catalyst-free. In this work, the use of highly lattice-mismatched GaAs/InxGa1-xAs and GaAs/InxAl1-xAs core/shell nanowires on Si(111) substrates have been studied as an alternative to InxGa1-xAs nanowires. The core/shell mismatch strain and its accommodation within the nanowires plays an important role in the growth, the structural, and the electronic properties of the nanowires. A key parameter in this work was the unusually small diameter of 20 – 25 nm of the GaAs core. First, the strain-induced bending of the nanowires during the growth of the shell by molecular beam epitaxy was investigated. It was apparent that the nanowires bend as a result of a preferential incorporation of In adatoms on one side of the nanowires. To obtain straight nanowires with symmetric shell composition and thickness around the core, it was necessary to choose relatively low growth temperatures and high growth rates that limited the surface diffusivity of In adatoms. Second, the strain accommodation in straight nanowires was investigated as a function of the shell thickness and composition using a combination of Raman scattering spectroscopy and X-ray diffraction. For a fixed shell composition of x=0.20 and small enough shell thicknesses, the strain in the shell is compressive and decreases progressively as the shell grows thicker. On the other hand, the strain in the core is tensile with hydrostatic character and increases with shell thickness. Finally, for shell thicknesses larger than 40 nm, the shell becomes strain-free, whereas the strain in the core saturates at 3.2% without any dislocations. For a fixed shell thickness of 80 nm, the strain in the core was further increased by increasing the In-content in the shell, reaching values as high as 7% for x=0.54. A plastic relaxation via misfit dislocations was observed only for the next highest In-content of x=0.70. In agreement to theoretical predictions, the tensile strain in the core resulted in a large reduction of the GaAs bandgap (as measured by photoluminescence spectroscopy), up to approximately 40% of the strain-free value. A similar reduction in electron effective mass is also expected. The transport properties of electrons inside the strained GaAs core were assessed by optical-pump terahertz-probe spectroscopy. Quite high mobility values of approximately 6100 cm2/Vs at 300 K for a carrier concentration of 9×1017 cm−3 were measured, which are the highest reported in the literature for GaAs nanowires, but also higher than the values for unstrained bulk GaAs. The importance of the results in this work is two-fold. On the one hand, strain-free InxGa1-xAs nanowire shells were grown on Si substrates with x up to 0.54 and thicknesses well beyond the critical thickness of their thin film counterparts. Such shells could potentially be employed as conduction channels in high electron mobility transistors (HEMTs) integrated in Si platforms. On the other hand, highly tensile-strained GaAs cores with electronic properties like those of InxGa1-xAs thin films were obtained. In this case, the results demonstrate, that GaAs nanowires can be suitable for photonic devices across the near-infrared range, including telecom photonics at 1.3 and potentially 1.55 μm, as well as for high-speed electronics. GaAs as a binary material is expected to be advantageous compared to InxGa1-xAs due to the absence of structural imperfections typically present in ternary alloys. Finally, to explore the potential of the core/shell nanowires as HEMTs, self-consistent Schrödinger-Poisson calculations of two different modulation-doped heterostructures were performed. In the case of a strained GaAs core overgrown by an unstrained InxGa1-xAs shell and an additional unstrained Si-doped InxAl1-xAs shell, the possibility to form a cylindrical-like two-dimensional electron gas inside the InxGa1-xAs shell was found. In the alternative case of a strained GaAs core overgrown by an unstrained Si-doped InxAl1-xAs shell, it was found that it is possible to form a quasi-one-dimensional electron gas at the center of the core. Both structures are the subject of ongoing research.:1 Introduction 1 2 Fundamentals and state-of-the-art 7 2.1 Electronic and structural properties of III-V semiconductors 7 2.2 Growth of III-V nanowires on Si 20 2.3 Core/shell heterostructure nanowires 29 2.4 Strain in epilayers and core/shell nanowires 36 2.5 Strain engineering in core/shell nanowires and its effect on band parameters 46 2.6 Modulation-doped III-V semiconductor heterostructures 56 3 Methods 61 3.1 Optical and electron microscopes 61 3.2 X-ray diffraction 64 3.3 Raman scattering spectroscopy 65 3.4 Photoluminescence spectroscopy 75 3.5 Optical-pump terahertz-probe spectroscopy and photoconductivity in semiconductors 77 3.6 Device processing 82 3.7 Semiconductor nanodevice software “nextnano” 85 3.8 MBE for crystal growth and core/shell nanowire growth 86 4 Results and discussions 91 4.1 Structural, compositional analyses of straight nanowires and coherent growth limit 91 4.2 Bent nanowires 95 4.3 Strain analyses in core/shell nanowires 97 4.3.1 Dependence of strain on shell thickness 97 4.3.2 Dependence of strain on the shell chemical composition 102 4.3.3 Dependence of strain on the core diameter 105 4.4 Strain-induced modification of electronic properties 106 4.5 Strain-enhanced electron mobility of GaAs nanowires higher than the bulk limit 114 4.6 Towards high electron mobility transistors 123 5 Conclusion and outlook 129 Bibliography 131 List of abbreviations I List of Symbols III List of publications VII List of conference contributions VIII Acknowledgements X
Ferroelectric Tunnel Junctions based on Ferroelectric-Dielectric Hf₀.₅Zr₀.₅O₂/Al₂O₃ Capacitor StacksMax, Benjamin, Hoffmann, Michael, Slesazeck, Stefan, Mikolajick, Thomas 29 November 2021 (has links)
We report on a two-layer based ferroelectric tunnel junction with hafnium zirconium oxide (HZO) as the ferroelectric layer and aluminum oxide as the tunneling layer. The experimental results focus on optimizing the thicknesses of the layer stack. The device operation relies on the polarization reversal of the HZO layer, while electron tunneling occurs through the dielectric layer. The ferroelectric response of the HZO shows high remanent polarization values and good endurance with only weak wake-up and fatigue behavior. Adding the additional dielectric tunneling layer, the device becomes operational as a ferroelectric tunnel junction in the nanoampere current range. It shows good on/off ratios and promising retention behavior, paving the way for future applications as a polarization-based resistive memory device.
Bimberg, D., Mikolajick, T., Wallart, X.
10 December 2021
The feasibility of the QD-Flash concept, its fast write and erase times, is demonstrated together with storage times of 4 days at room temperature. The storage time of holes in (InGa)Sb QDs embedded in a (AlGa)P matrix can be extended by growth modifications to 10 y. Tunneling structures were recently demonstrated to solve the trade-off conflict between storage time and erase time. A QD-NVSRAM is suggested to become the first commercial application.
24 November 2021
The number of subscribers and use cases of mobile communication networks are expanding expeditiously with the evolution of technology. The available spectrum in lower frequency ranges does not meet the unprecedented increase in demand for user data throughput in mobile networks. Facing the problem of limited spectrum in traditional cellular bands that are below 6 GHz, Millimeter Wave (mmWave) frequency bands are being standardized for the 5th Generation (5G) mobile networks as a promising means for handling the unprecedented data traffic surge. Enabling higher carrier frequencies introduces new channel conditions. Propagating signals are exposed to higher diffraction loss and are highly susceptible to blockage caused by surrounding objects, which leads to rapid signal degradation and challenges user mobility. On the other hand, higher carrier frequencies enable the deployment of many small-sized antennas that are used for directional signal transmission, resulting in beamforming gain. In recent studies, a conditional handover procedure has been adopted for 5G networks to enhance user mobility robustness. Besides, contention-free random access procedure has been defined for beamformed systems aiming at minimizing the signaling and service interruption time caused by the random access procedure. An improper configuration of the mobility parameters, e.g., handover preparation and execution offsets, access beam selection threshold of random access procedure, leads User Equipments (UEs) to experience Handover Failures (HOFs) and Radio Link Failures (RLFs), and causes unnecessary signaling and inefficient resource utilization in the network. Each cell border has unique propagation characteristics and user mobility pattern, and, therefore, mobility parameters should be configured for each cell border individually. Moreover, mobility parameters should be updated for dynamic propagation environment (e.g., construction of buildings, seasonal changes in the vegetation) and for temporal mobility patterns. Considering the individual cell border configuration, temporal adaptation of the mobility parameters, and ultra-dense deployment, optimization of the conditional handover and random access parameters is a complex task that cannot be carried by human interaction. Therefore, an automatic optimization of the parameters is needed where the network collects statistics of the mobility events and adjusts the parameters autonomously. To investigate user mobility under these new propagation conditions, a proper model is needed that captures spatial and temporal characteristics of the channel in beamformed networks. Current channel models that have been developed for 5G networks are too detailed for the purpose of mobility simulations and lead to infeasible simulation time for most user mobility simulations. In this work, a simplified channel model is presented that captures the spatial and temporal characteristics of the 5G propagation channel and runs in feasible simulation time. To this end, the coherence time and path diversity originating from a fully fledged Geometry-based Stochastic Channel Model (GSCM) are analyzed and adopted in Jake’s channel model with reduced computational complexity. Furthermore, the deviation of multipath beamforming gain from single ray beamforming gain is analyzed and a regression curve is obtained to be used in the system-level simulations. In a typical system-level mobility simulator, the average downlink signal-to-interference and noise ratio (SINR) is used for RLF detection and throughput calculation. In addition to the channel model, models of desired and interfering signals are formulated first, by considering the impact of antenna beamforming, and a closed-form expression of average downlink SINR is derived by taking into account the user and beam scheduling probabilities. Then, an accurate approximation of the average downlink SINR with low computational complexity is presented, for 5G networks where the base station forms multiple beams. In addition, an SINR model is derived for both strict and opportunistic resource-fair scheduler, where the latter targets a higher utilization of radio resources when multiple beams are scheduled simultaneously. The mobility performance of conditional handover and contention-free random access are investigated by using the proposed channel and SINR models. Besides, a resource efficient random access procedure is proposed that aims at maximizing the utilization of contention-free random access resources. Moreover, simple, yet, effective decision tree-based supervised learning method is proposed to minimize the HOFs that are caused by the beam preparation phase of the random access procedure. Similarly, a decision-tree-based supervised learning method is proposed for automatic optimization of the conditional handover parameters. In addition, enhanced logging and emergency reporting methods are introduced first time in this study to mitigate the cell detection problems that are caused by rapid signal degradation. Results show that the optimum operation point of random access (in terms of minimizing the HOFs and maximizing the random access resource utilization) is achievable with the proposed learning algorithm for random access procedure in conditional handover. Results also show that the mobility performance of conditional handover is improved by automatic optimization of the handover parameters. In addition, the proposed enhanced logging and emergency reporting methods mitigate the mobility problems related with cell detection and further improve the mobility performance in combination with the decision-tree-based supervised learning methods.
Page generated in 0.1543 seconds