Flexible electronics has attracted significant attention in the recent past due to the booming wearables market in addition to the ever-increasing interest for faster, thinner and foldable mobile phones. Ultra-thin bare silicon ICs fabricated by thinning down standard ICs to thickness below 50 μm are flexible and therefore they can be integrated on or in polymer foils to create flexible hybrid electronic (FHE) components that could be used to replace rigid standard surface mount device (SMD) components. The fabricated FHE components referred as chip foil packages (CFPs) in this work are ideal candidates for FHE system integration owing to their ability to deliver high performance at low power consumption while being mechanically flexible. However, very limited information is available in the literature regarding the reliability of CFPs under static and dynamic bending. The lack of such vital information is a major obstacle impeding their commercialization. With the aim of addressing this issue, this thesis investigates the static and dynamic bending reliability of CFPs. In this scope, the static bending reliability of CFPs has been investigated in this thesis using flexural bending tests by measuring their fracture strength. Then, Finite Element Method (FEM) simulations have been implemented to calculate the fracture stress of ultra-thin flexible silicon chips where analytical formulas may not be applied. After calculating the fracture stress from FEM simulations, the enhancement in robustness of ultra-thin chips (UTCs) against external load has also been proved and quantified with further experimental investigations. Besides, FEM simulations have also been used to analyse the effect of Young’s Modulus of embedding materials on the robustness of the embedded UTCs. Furthermore, embedding the UTCs in polymer layers has also been experimentally proven to be an effective solution to reduce the influence of thinning and dicing induced damages on the robustness of the embedded UTCs. Traditional interconnection techniques such as wire bonding may not be implemented to interconnect ultra-thin silicon ICs owing to the high mechanical forces involved in the processes that would crack the chips. Therefore, two novel interconnection methods namely (i) flip-chip bonding with Anisotropic Conductive Adhesive (ACA) and (ii) face-up direct metal interconnection have been implemented in this thesis to interconnect ultra-thin silicon ICs to the corresponding interposer patterns on foil substrates. The CFP samples thus fabricated were then used for the dynamic bending reliability investigations. A custom-built test equipment was developed to facilitate the dynamic bending reliability investigations of CFPs. Experimental investigations revealed that the failure of CFPs under dynamic bending was caused mainly by the cracking of the redistribution layer (RDL) interconnecting the chip and the foil. Furthermore, it has also been shown that the CFPs are more vulnerable to repeated compressive bending than to repeated tensile bending. Then, the influence of dimensional factors such as the thickness of the chip as well as the RDL on the dynamic bending reliability of CFPs have also been studied. Upon identifying the plausible cause behind the cracking of the RDL leading to the failure of the CFPs, two methods to improve the dynamic bending reliability of the RDL have been suggested and demonstrated with experimental investigations. The experimental investigations presented in this thesis adds some essential information to the state-of-the-art concerning the static and the dynamic bending reliability of UTCs integrated in polymer foils that are not yet available in the literature and aids to establish in-depth knowledge of mechanical reliability of the components required for manufacturing future FHE systems. The strategies devised to enhance the robustness of UTCs and CFPs could serve as guidelines for fabricating reliable FHE components and systems.

There is always a need for more compact designs of power transformers free of partial discharges, in order to save cost on the construction and required material resources. The physical geometric constrictions inside the transformer tank would demand field-grading techniques to homogenise the field strength distribution on oil-solid interfaces, when required. Standard filler materials such as carbon black or silicon carbide (SiC) have a too high electrical conductivity yielding an appropriate grading field strength values for air-related applications. Because insulation oil has a higher electrical breakdown strength, the electrical conductivity must be engineered to lower values in order to reach a higher effective grading field strength. This paper presents the investigation of a new material system based on a phenolic resin Lerg FL-500 and the electrically functionalized ceramic filler particles Merck Iriotec®7550 that enable a resistive electrical field grading in insulation oil. In order to verify the principle functionality of the proposed field grading system, a layer is applied on a substrate surface representing possible oil-solid-interface inside oil-filled power transformers. First, the manuscript describes the methods of specimen preparation and the measurement of the nonlinear current-time behaviour under AC voltage stress for different filler contents. Second, a concurring optical and electrical determination of the partial discharge inception and extinction voltage of a modified Toepler arrangement allows the indirect determination of the electrical field strength distribution along the functionalized layer without the need of direct measurement. To do so, the radius of the circular functional layer is varied and with it the specific grading length. In analogy to state of the art SiC-filled systems, a linear dependency between the effective grading length and the PD inception voltage is observed. The quotient of voltage drop over a varied radius yields the effective graded electric field strength.

Main goal of this thesis is evaluation of the available SON and sacrificial layer technologies from the perspective of temperature sensor design. Based on the findings, a series of detector architectures is proposed. The work is subdivided into two major parts, with the first one targeting the process characterization. Good command of the selected technology, awareness of its dependencies and limitations, is essential and has to be examined prior to any MEMS design. Pressure related topics are of particular interest, since this criterion, among others, highly influences the performance of thermal systems. Knowledge of the critical parameters is applied in the second half, where the actual IR sensor design is considered. Process characterization, required for thermal insulation estimations, is not the only link between the two physics fields. Discussed IR detectors are highly inspired by the developed pressure sensing solutions. This resulted in either similar operation principles being applied, or even the same fabricated structures being adapted for new use.:List of abbreviations List of Figures List of Tables Acknowledgements 1 Introduction 1.1 Motivation and organization of the work 1.2 Microstructure fabrication methods 1.2.1 Surface micromachining 1.2.2 Bulk micromachining 1.2.3 SOI and SON structuring 2 Pressure sensor for process characterization applications 2.1 Motivation 2.2 Pirani gauge approach 2.2.1 Principles of operation and state of the art 2.2.2 Modelling 2.2.2.1 Setup 2.2.2.2 Results 2.2.3 Processing 2.2.4 Measurement 2.2.4.1 Setup 2.2.4.2 Results 2.2.5 Application 2.2.5.1 Outgassing characterization 2.2.5.2 Reliability investigation 2.2.5.3 Thermal emitter for IR spectroscopy 2.2.5.4 Active pressure sensor 2.3 Capacitive sensor approach 2.3.1 Principles of operation and state of the art 2.3.2 Surface channel approach 2.3.3 SON channel approach 2.3.4 Application 2.3.4.1 MEMS dynamic characterization 2.3.4.2 Differential capacitive pressure sensor 2.4 Summary and overview of results 3 Temperature sensor for IR applications 3.1 Motivation 3.2 Resistive sensor approach 3.2.1 Principles of operation 3.2.2 Modelling 3.2.3 Measurement 3.3 Capacitive sensor approach 3.3.1 Principles of operation 3.3.2 Modelling 3.3.2.1 Setup 3.3.2.2 Results 3.3.3 Processing 3.4 Junction - based approach 3.4.1 State of the art 3.4.2 Thermal insulation design 3.4.2.1 Overview 3.4.2.2 Processing 3.4.2.3 Thermal performance 3.4.3 Detector design 3.4.3.1 Diode sensing solution 3.4.3.2 Bipolar Junction Transistor sensing solution 3.4.3.3 Junction Field Effect Transistor sensing solution 3.5 Summary and overview of results 4 Conclusion Bibliography

Diese Dissertation behandelt schwache Nichtlinearitäten in Radiofrequenzschaltern, die auf Grundlage von CMOS-Transistoren realisiert werden. Der besondere Schwerpunkt liegt auf der analytischen Modellierung sowie der Simulation der Nichtlinearität mithilfe einer TCAD (Technology Computer-Aided Design) Software. Die Nichtlinearität kann nach den verschiedenen Quellen klassifiziert werden: der Transistornichtlinearität und der Substratnichtlinearität. Für beide Bereiche werden umfassende Simulationen und analytische Modellierungen sowie Messungen präsentiert und interpretiert. / This dissertation treats weak nonlinearities in radio frequency switches that are realised based on CMOS transistor technology. A special focus lies on the analytical modeling and TCAD simulation of the nonlinearity. The nonlinearity is sorted into substrate and transistor nonlinearity. For both nonlinear regions profound simulations, analytical modeling and measurements are presented and interpreted.

This paper deals with a method to additionally heat with switching losses in a classical power cycling test, as it is often used for power semiconductors.The fundamentals of testing, switching behavior, thermal and electrical characteristics of semiconductors are covered.The core of the work is the construction, start-up and solution of technical problems during the testing of the test stand. Another aspects are the measurement and software challenges in generating the pulse pattern and in evaluating the results. The last part of the work deals with the testing of different types of semiconductors, such as IGBTs and MOSFETs, which were also made of different materials, such as silicon and silicon carbide, and had different voltage classes.:Contents i Symbols and Abbreviations iii Introduction 1 1. Power Cycling Lifetime 2 1.1. Power Cycling-induced Ageing Mechanisms and Test Methods 2 1.1.1. Overview of Packaging Technologies and their Wear-out Failures 2 1.1.2. Failure Mechanisms in Power Modules and Discrete Devices 6 1.1.3. Basic Structure of a Test Bench for DC Power Cycling Tests 8 1.1.4. Modifications for SiC MOSFET Operation 12 1.1.5. Measurement Accuracy, Limits and Consequences for Test Evaluation 16 1.1.6. Thermal Resistance and Thermal Impedance Spectroscopy 18 1.2. Empirical Power Cycling Lifetime Models 21 2. Specific Limitations in Conditions for some Devices 27 3. Approaches of an Application-close Power Cycling Test 30 4. New Test Bench Concept with an adjustable part of switching losses 35 4.1. Basics for Switching 35 4.1.1. Active Clamping 38 4.1.2. Boosted Active Clamping 40 4.2. Repetitive Unclamped Inductive Switching 42 4.3. Test Bench Concept for Power Cycling Test with Turn-off Losses 44 4.4. Dimensioning of the Stray Inductance 47 4.4.1. Current Ripple and Attainable Switching Losses 51 4.5. Special Setup for Si and SiC MOSFETs 57 4.6. Measurement Algorithm and necessary Hardware 58 4.6.1. Measurement Hardware 58 4.6.2. Measurement Algorithm 60 4.6.3. Challenges during the Measurement 62 4.6.4. Current Source for Fast Regulation 66 5. Test Results with IGBTs 69 5.1. Modules with Baseplate 69 5.2. Modules without Baseplate 80 5.3. IGBTs in Discrete Housings 90 6. Test Results with MOSFETs 97 6.1. Low Voltage Si MOSFETs 97 6.2. SiC MOSFETs 106 7. Analysis of Si Low-voltage MOSFETs Results with FEM 107 8. Conclusion and Outlook 113 9. Acknowledgement 118 References 119 Appendix 136

Ausgangspunkt vorliegender Arbeit sind Ergebnisse aus vorangehenden lichttechnischen Projekten (Einsatz von LED und OLED in elektrischen Bahnen) sowie die Beteiligung am Forschungsprojekt NiviL. In dessen Teilprojekt 'Melatoninsuppression und Phasenverschiebung', welches in Kooperation mit dem Universitätsklinikum Dresden bearbeitet wurde, sind in zwei medizinischen Studien der Einfluss unterschiedlicher Lichtspektren auf jeweils zwei Probandengruppen untersucht worden: gesunde Kontrollprobanden und Probanden mit einer Bipolar-I-Störung. Um die Effekte der Lichtspektren nachweisen zu können, wurden flexibel konfigurierbare Beleuchtungseinheiten entworfen, welche die Retina im Auge des Betrachters gleichmäßig und vollständig ausleuchten. Das Ziel, eine sehr gute Homogenität der Exposition sowie Flimmerfreiheit reproduzierbar sicherzustellen, wurde durch spezielle, mit neuartigen Konzepten entwickelte LED-Treiber mit intelligenter Konstantstrom- und PWM-Dimmung erreicht. Es konnte mittels einer Farbortregelung in der ersten Studie und einer, von der Pupillengröße abhängigen, Leuchdichteregelung in der zweiten Studie eine optimale Versuchsdurchführung durch die Eliminierung unerwünschter Einflussfaktoren wie Helligkeitsschwankungen oder unterschiedliche Pupillengrößen gewährleistet werden. In den Studien wurden zwei Probandengruppen untersucht: gesunde Kontrollprobanden und Probanden mit einer Bipolar-I-Störung. Die Hypothese der ersten Studie geht von einer verstärkten Melatoninsuppression sowie einer verminderten Müdigkeit der bipolaren Probanden während einer Exposition mit blauem Licht im Vergleich zu gesunden Kontrollprobanden aus. In der zweiten Studie wurde die Hypothese einer verstärkten Phasenverschiebung der 'inneren Uhr' der Probanden mit Bipolar-I-Störung gegenüber der Kontrollgruppe überprüft. Studiendesign, Methodik, Durchführung und Auswertung der Probandenstudien sind umfassend dokumentiert worden. Während der Untersuchungen wurden folgende Parameter gemessen: Melatoninspiegel im Blut, Elektroenzephalogramm, Herzfrequenz und Herzratenvariabilität, Pupillenunruhe sowie der Karolinska-Schläfrigkeitswert (KSS). Diese wurden aus ingenieurtechnischer Sicht eingeführt, die damit gemessenen Daten statistisch ausgewertet und abschließend hinsichtlich ihrer Aussagekraft und Anwendbarkeit zur objektiven Quantifizierung nichtvisueller Wirkungen beurteilt.

The concept of network slicing has been introduced in order to enable mobile networks to accommodate multiple heterogeneous use cases that are anticipated to be served within a single physical infrastructure. The slices are end-to-end virtual networks that share the resources of a physical network, spanning the core network (CN) and the radio access network (RAN). RAN slicing can be more challenging than CN slicing as the former deals with the distribution of radio resources, where the capacity is not constant over time and is hard to extend. The main challenge in RAN slicing is to simultaneously improve multiplexing gains while assuring enough isolation between slices, meaning one of the slices cannot negatively influence other slices. In this work, a flexible and configurable framework for RAN slicing is provided, where diverse requirements of slices are taken into account, and slice management algorithms adjust the control parameters of different radio resource management (RRM) mechanisms to satisfy the slices' service level agreements (SLAs). A new entity that translates the key performance indicator (KPI) targets of the SLAs to the control parameters is introduced and is called RAN slice orchestrator. Diverse algorithms governing this entity are introduced, which range from heuristics-based to model-free methods. Besides, a protection mechanism is constructed to prevent the negative influences of slices on each other's performances. The simulation-based analysis demonstrates the feasibility of slicing the RAN with multiplexing gains and slice isolation.

Future 6G wireless communications network will increase the data capacity to unprecedented numbers and thus empower the deployment of new real-time applications. Millimeter-Wave (mmWave) band and Massive MIMO are considered as two of the main pillars of 6G to handle the gigantic influx in data traffic and number of mobile users and IoT devices. The small wavelengths at these frequencies mean that more antenna elements can be placed in the same area. Thereby, high spatial processing gains are achievable that can theoretically compensate for the higher isotropic path loss. The propagation characteristics at mmWave band, create sparse channels in typical scenarios, where only few paths convey significant power. Considering this feature, Hybrid (analog-digital) Beamforming introduces a new signal processing framework which enables energy and cost-efficient implementation of massive MIMO with innovative smart arrays. In this setup, the analog beamalignment via beam selection in link access phase, is the critical performance limiting step. Considering the variable operating condition in mmWave channels, a desirable solution should have the following features: efficiency in training (limited coherence time, delay constraints), adaptivity to channel conditions (large SNR range) and robustness to realized channels (LOS, NLOS, Multipath, non-ideal beam patterns). For the link access task, we present a new energy-detection framework based on variable length channel measurements with (orthogonal) beam codebooks. The proposed beam selection technique denoted as composite M-ary Sequential Competition Test (SCT) solves the beam selection problem when knowledge about the SNR operating point is not available. It adaptively changes the test length when the SNR varies to achieve an essentially constant performance level. In addition, it is robust to non-ideal beam patterns and different types of the realized channel. Compared to the conventional fixed length energy-detection techniques, the SCT can increase the training efficiency up to two times while reducing the delay if the channel condition is good. Having the flexibility to allocate resources for channel measurements through different beams adaptively in time, we improve the SCT to eliminate unpromising beams from the remaining candidate set as soon as possible. In this way, the Sequential Competition and Elimination Test (SCET) significantly further reduces training time by increasing the efficiency. The developed ideas can be applied with different codebook types considered for practical applications. The reliable performance of the beam selection technique is evident through experimental evaluation done using the state-of-the-art test-bed developed at the Vodafone Chair that combines a Universal Software Radio Peripheral (USRP) based platform with mmWave frontends.

In dieser Arbeit wird eine genaue Zeitsynchronisation über kupferbasierte Ethernetsysteme sowie der Entwurf von Schaltungen für die Bitübertragungsschicht (Physical Layer, PHY) in solchen Ethernetsystemen untersucht. Dabei wird der Entwurf eines integrierten Schaltkreises für den Standard 100Base-TX vorgestellt. Dieser PHY-Chip ermöglicht die Datenübertragung mit einer Datenrate von 100 MBit/s über verdrillte Kupferkabel und stellt darüber hinaus eine genaue Uhr bereit, welche zwischen den verbundenen Netzknoten synchronisiert werden kann. Dieser Schaltkreis ist insbesondere für Industrieanwendungen gedacht, bei denen verschiedene Prozesse zeitlich synchronisiert werden müssen. Prinzipiell ist der PHY-Chip jedoch universell für verschiedenste Anwendungen zur Zeitsynchronisation einsetzbar. Um die Genauigkeit der Zeitsynchronisation gegenüber herkömmlichen Ansätzen zu steigern, werden verschiedene Techniken untersucht und in dem entworfenen Schaltkreis eingesetzt. So wird die Phase der Taktsignale in feinen Schritten eingestellt und auch gemessen, sodass die Auflösung der Zeitstempel erheblich verbessert wird. Zu diesem Zweck wird ein sogenannter Digital-To-Phase Converter (DPC) eingesetzt, der 256 verschiedene Taktphasen des 125 MHz Systemtaktes bereitstellt. Für die eigentliche Zeitsynchronisation wird ein Proportional-Integral-Regler verwendet. Basierend auf einer theoretischen Rauschanalyse wird eine Methode vorgestellt, mit der die Parameter dieses Reglers so dimensioniert werden können, dass der Zeitfehler im eingeschwungenen Zustand möglichst klein wird. Darüber hinaus werden weitere Störeinflüsse analysiert und es werden geeignete Maßnahmen entwickelt, um diese zu kompensieren. So wird eine adaptive Kompensation eines Eintonstörers sowie eine Kalibrierung zur automatischen Kompensation von Asymmetrien im Kabel vorgestellt. All diese Punkte helfen, eine hervorragende Genauigkeit der Zeitsynchronisation zu ermöglichen, was durch umfangreiche Messungen verifiziert wird. Insgesamt weist der gemessene Zeitfehler in einem Punkt-zu-Punkt-Szenario eine Standardabweichung von 64 ps und einen Mittelwert unterhalb von 100 ps auf. Dies stellt eine erhebliche Verbesserung gegenüber konventionellen Lösungen zur Zeitsynchronisation über kupferbasiertes Ethernet dar, mit denen Genauigkeiten im Nanosekundenbereich erreicht werden. Als zweites Ziel dieser Arbeit wird der PHY-Chip für eine möglichst niedrige Leistungsaufnahme optimiert. Um dies zu erreichen, werden insbesondere der Leitungstreiber im Sender und der Equalizer im Empfänger systematisch optimiert. So werden zwei verschiedene Topologien von Leitungstreibern untersucht und verglichen. Beide weisen eine Leistungsaufnahme von etwa 24 mW auf. Im Vergleich zum Stand der Technik sind dies die beiden niedrigsten Werte für Leitungstreiber für den Standard 100Base-TX. Der gesamte PHY-Chip, der in einer 180 nm Technologie implementiert wurde, weist durch die zahlreichen Optimierungen eine geringe Leistungsaufnahme von maximal 69 mW auf, was ebenfalls einen Rekordwert im Vergleich mit dem Stand der Technik darstellt (80 mW). Die einzelnen Schaltungen wurden sowohl simulativ als auch mit ausführlichen Messungen verifiziert. Für den gesamten Link wird eine Bitfehlerrate besser als 10⁻¹² bei verschiedenen Kabeln bis zu 120 m Länge erreicht.:Abbildungsverzeichnis Tabellenverzeichnis Abkürzungen Symbole 1 Einleitung 1.1 Zeit und Zeitsynchronisation 1.2 Ziele dieser Arbeit 1.3 Gliederung 2 Grundlagen 2.1 100Base-TX Ethernet-Standard 2.1.1 Schnittstelle zur MAC-Schicht 2.1.2 4B5B-Kodierung 2.1.3 Scrambler und Descrambler 2.1.4 MLT-3-Kodierung 2.1.5 Bitfehlerrate und Signal-Rausch-Verhältnis 2.2 Kanalmodellierung 2.2.1 Dämpfung 2.2.2 Baseline-Wander 2.3 Zeitsynchronisierung 2.3.1 Bestimmung der Zeitdifferenz 2.3.2 Vergrößerung der Synchronisationsgenauigkeit 3 Schaltungsentwurf und Charakterisierung 3.1 Energieeffiziente Leitungstreiber 3.1.1 Vergleich von Leitungstreibern mit passiver Anpassung 3.1.2 Spannungstreiber 3.1.3 Leitungstreiber mit aktiver Anpassung 3.1.4 Vergleich der Leitungstreiber und Fazit 3.2 Takterzeugung 3.2.1 Ringoszillator 3.2.2 Phasenregelschleife 3.2.3 Phaseninterpolator 3.2.4 Messung 3.2.5 Verbesserter 10 Bit DPC 3.3 Takt- und Datenrückgewinnung 3.3.1 Phasendetektor 3.3.2 Modellierung des DPC 3.3.3 Dimensionierung des Schleifenfilters 3.3.4 Implementierung 3.4 Adaptiver Equalizer 3.4.1 Kompensation der Kabeldämpfung 3.4.2 Implementierung des analogen Filters 3.4.3 Digitale Regelung der Equalizer-Parameter 3.4.4 Messung des Equalizers 3.5 Zeitsynchronisation 3.5.1 Uhr und Steuerung der Frequenz 3.5.2 Digitale Schaltungen zur Zeitstempelung 3.5.3 Implementierung der Zeitsynchronisation 3.5.4 Adaptive Unterdrückung eines Eintonstörers 3.5.5 Automatische Kalibrierung von Asymmetrien 3.5.6 Vergleich mit dem Stand der Technik 3.6 Gesamter PHY-Schaltkreis 3.6.1 Leistungsaufnahme 3.6.2 Vergleich mit dem Stand der Technik 4 Zusammenfassung und Ausblick Literaturverzeichnis Eigene Veröffentlichungen / This work investigates accurate time synchronization over copper-based Ethernet systems as well as the design of circuits for the physical layer (PHY) in such Ethernet systems. The design of an integrated circuit (IC) for the 100Base-TX standard is presented. This PHY-IC enables data transmission at a data rate of 100 MBit/s over twisted pair copper cables and, additionally, provides an accurate clock which can be synchronized between connected network nodes. This circuit is designed for industrial applications where various processes need to be synchronized in time. In principle, however, the PHY-IC can be used universally for various time synchronization applications. In order to increase the accuracy of the time synchronization compared to conventional approaches, various techniques are investigated and used in the designed circuit. For example, the phase of the clock signals is adjusted and measured in fine steps, such that the resolution of the timestamps is improved by a large amount. For this purpose, a digital-to-phase converter (DPC) is used, which provides 256 different clock phases of the 125 MHz system clock. A proportional integral controller is used for the actual time synchronization application. Based on a theoretical noise analysis, a method is presented to dimension the parameters of this controller to minimize the timing error in the steady state. Furthermore, other disturbing influences are analyzed and suitable measures are developed to compensate them. Thus, an adaptive compensation of a single-tone interferer is presented as well as a calibration to automatically compensate for asymmetries in the cable. All these points help to provide excellent accuracy of the time synchronization, which is verified by extensive measurements. Overall, the measured time error in a point-to-point scenario has a standard deviation of 64 ps and a mean value below 100 ps. This represents a significant improvement over conventional solutions for time synchronization over copper-based Ethernet, which achieve accuracies in the nanosecond range. As a second goal of this work, the PHY-IC is optimized for lowest power consumption. In particular, the line driver in the transmitter and the equalizer in the receiver are systematically optimized to achieve this. Thus, two different topologies of line drivers are investigated and compared. Both have a power consumption of about 24 mW. These represent the two lowest values for line drivers for the 100Base-TX standard compared to the state of the art. The entire PHY-IC is implemented in a 180 nm technology and shows a power consumption below 69 mW due to the numerous optimizations. This also represents a record value compared to the state of the art (80 mW). The individual circuits were verified with simulations and with detailed measurements. For the entire link, a bit error rate better than 10⁻¹² is achieved for various cables up to 120 m length.:Abbildungsverzeichnis Tabellenverzeichnis Abkürzungen Symbole 1 Einleitung 1.1 Zeit und Zeitsynchronisation 1.2 Ziele dieser Arbeit 1.3 Gliederung 2 Grundlagen 2.1 100Base-TX Ethernet-Standard 2.1.1 Schnittstelle zur MAC-Schicht 2.1.2 4B5B-Kodierung 2.1.3 Scrambler und Descrambler 2.1.4 MLT-3-Kodierung 2.1.5 Bitfehlerrate und Signal-Rausch-Verhältnis 2.2 Kanalmodellierung 2.2.1 Dämpfung 2.2.2 Baseline-Wander 2.3 Zeitsynchronisierung 2.3.1 Bestimmung der Zeitdifferenz 2.3.2 Vergrößerung der Synchronisationsgenauigkeit 3 Schaltungsentwurf und Charakterisierung 3.1 Energieeffiziente Leitungstreiber 3.1.1 Vergleich von Leitungstreibern mit passiver Anpassung 3.1.2 Spannungstreiber 3.1.3 Leitungstreiber mit aktiver Anpassung 3.1.4 Vergleich der Leitungstreiber und Fazit 3.2 Takterzeugung 3.2.1 Ringoszillator 3.2.2 Phasenregelschleife 3.2.3 Phaseninterpolator 3.2.4 Messung 3.2.5 Verbesserter 10 Bit DPC 3.3 Takt- und Datenrückgewinnung 3.3.1 Phasendetektor 3.3.2 Modellierung des DPC 3.3.3 Dimensionierung des Schleifenfilters 3.3.4 Implementierung 3.4 Adaptiver Equalizer 3.4.1 Kompensation der Kabeldämpfung 3.4.2 Implementierung des analogen Filters 3.4.3 Digitale Regelung der Equalizer-Parameter 3.4.4 Messung des Equalizers 3.5 Zeitsynchronisation 3.5.1 Uhr und Steuerung der Frequenz 3.5.2 Digitale Schaltungen zur Zeitstempelung 3.5.3 Implementierung der Zeitsynchronisation 3.5.4 Adaptive Unterdrückung eines Eintonstörers 3.5.5 Automatische Kalibrierung von Asymmetrien 3.5.6 Vergleich mit dem Stand der Technik 3.6 Gesamter PHY-Schaltkreis 3.6.1 Leistungsaufnahme 3.6.2 Vergleich mit dem Stand der Technik 4 Zusammenfassung und Ausblick Literaturverzeichnis Eigene Veröffentlichungen

The polarization reversal in ferroelectric HfO₂ is adopted to store information in three distinct device classes - ferroelectric field effect transistors (FeFET), ferroelectric capacitors (FeCAP) and ferroelectric tunnel junctions (FTJ). Common to all three concepts is the adoption of a ferroelectric layer stack that acts either as gate dielectric in the FeFET or as the capacitor dielectric and tunneling barrier in the FeCAP or FTJ, respectively. A composite structure including an inevitably or purposefully formed dielectric layer is frequently adopted. In this work we report on the co-existence of all three memory concepts within one device structure and propose a 2T1C ferroelectric memory cell that allows the operation and comparative characterization of the trinity of ferroelectric memory devices.