Global ETD Search

231	An assessment of dual-rail encoded on-line test methodologies and their impact on ASIC/FPGA design Thulborn, David January 1997 (has links) The testing of fabricated Integrated Circuits (IC's) is of great concern to production engineers and circuit designers alike. With the complexity of Very Large Scale Integrated (VLSI) circuits increasing every year, the problem of testing the fabricated designs is becoming acute. Several methods for reducing the burden of IC testing have been incorporated into the designs being tested thus giving rise to the phrase Design For Test (DFT). This thesis aims to understand how dual rail encoding of digital data can affect the different characteristics of electronic circuits. More specifically, it investigates a novel on-line test methodology called IFIS (If it Fails, It Stops), and its impact upon the design and implementation of electronic circuits intended for Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) technologies. The first two studies investigate the characteristics of the IFIS methodology to determine the most efficient and effective encoding scheme, protocol rules and feedback structures required for data processing. The third study investigates a series of possible improvements to the design of IFIS cells and determines the most efficient method of designing cells using the IFIS methodology. The final study investigates the feasibility of IFIS using a 'real life' commercial UART re-engineered using the IFIS methodology. The outcome of this work is an identification and characterisation of the factors which influence the performance and implementation cost of the IFIS methodology. 621.3192 Integrated circuits
232	Optimum MESFET frequency multiplier design Tang, Wing Ho Aaron January 1993 (has links) No description available. 621.3192 Integrated circuit design
233	Automating the MMIC design process using expert systems Brennan, Michael January 1993 (has links) No description available. 003.5 Microwave Integrated Circuit
234	CIM optimization / Tie, Hii Yong. Unknown Date (has links) Thesis (PhD) -- University of South Australia, 1992
235	Estimation of Analog Layout Parasitics with Parameterized Polygons Tseng, I-Lun Unknown Date (has links) No description available. 290902 Integrated Circuits
236	Nanometer VLSI placement and optimization for multi-objective design closure Luo, Tao, January 1900 (has links) Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references. Integrated circuits Algorithms.
237	Constraint solving over multi-valued logics application to digital circuits / Azevedo, Francisco. January 1900 (has links) Thesis (Ph. D.)--UNL/FCT. / Description based on print version record. Includes bibliographical references and index. Integrated circuits Digital electronics.
238	The testability of microprocessor systems : an assessment of signature analysis as a method of field-service / Liebelt, Michael John. January 1981 (has links) (PDF) Thesis (M.Eng.Sc.) - Dept. of Electrical Engineering, University of Adelaide. / Typescript (photocopy). Microprocessors Integrated circuits
239	A built-in self test (BIST) technique for single-event transient testing in digital circuits Balasubramanian, Anitha, January 2008 (has links) Thesis (M. S. in Electrical Engineering)--Vanderbilt University, Aug. 2008. / Title from title screen. Includes bibliographical references. Integrated circuits Radiation hardening.
240	Silicon Carbide JFET Integrated Circuit Technology for High-Temperature Sensors Patil, Amita C. January 2009 (has links) Thesis (Ph.D.)--Case Western Reserve University, 2009 / Abstract Department of Electrical Engineering Title from PDF (viewed on 20 April 2009) Available online via the OhioLINK ETD Center Integrated circuits. Silicon carbide.

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