Market variation such as changing utility price or demand can lead to non-static operation of chemical plants, such as in cases where new objectives must be met, or varying operating conditions can be taken advantage of to increase operational profit. Integrated design and control (where both the design and operation are considered simultaneously when the design of the plant is being formulated) can be used to address the challenges that plants that operate under uncertainty may face. When considering demand uncertainty for a plant, not only must the different realizations of demand be considered, but how the plant transitions from one demand to another is also of interest. Ideally when transitioning, the plant must quickly and feasibly transition from one operating point to another. In the first study of this thesis we consider the benefit of taking into account the demand transitions a plant must undergo; compared to only considering the final operating states. In this study we examine an air separation unit (ASU) since in industrial practice ASUs can often be subject to demand uncertainty. Assessing the impact that an ASU design has on its dynamic response characteristics motivates us to include plant dynamics in the design formulation. Using a two-stage stochastic optimization framework, the optimal design parameters are found for a nitrogen plant operating under uncertain demand. Three design paradigms are explored and compared - a nominal steady-state design, a flexible design that maintains steady-state feasibility, and a dynamically operable design that enforces feasibility of dynamic transitions. The designs obtained are subjected to random demand changes to evaluate the expected economic return under transitions not directly designed for. From this study we see that when the dynamically operable design and the flexible design are both subject to dynamic transitions, the dynamically operable design in certain cases can provide more economic benefit during transition and at the final steady state. In the second study of this thesis we address an important issue that arises when uncertainty in the plant operation is captured by utilizing two-stage stochastic optimization. If the optimization formulation can see the uncertainty profile in its entirety, then it can make control moves and design decisions based on the fact that the optimization problem knows what operating conditions it transitions between. This may not however be a realistic assumption to operate under, as future uncertainty is unknown. Given lack of foresight into future uncertainties it is logical to currently operate at the the optimal steady-state. This poses a bilevel problem for the design and control of a plant because the feasible region is determined by an inner optimization. In this study the Karush-Kuhn-Tucker conditions are incorporated into a two-stage stochastic optimization formulation for a dynamic model of chemical plant to generate a design. This design is then compared to a design generated from an optimization formulation where future knowledge of uncertainty is assumed and it is seen that the former design can provide greater economic benefit. / Thesis / Master of Applied Science (MASc)

Very low voltage, high current output requirement have necessitated improvements in power supply's density and efficiency. Existing power conversion techniques cannot meet very stringent size and efficiency requirements. By applying the proposed magnetic integration procedure, new integrated magnetic circuits featuring low loss, simple structure, and ripple cancellation technique are then developed to overcome the limitations of prior art. Both cores and windings are integrated. Consequently, the power loss and the size of the integrated magnetic device are greatly reduced. Detailed analysis and design considerations of the proposed circuits are presented. As a result of applying the proposed technique, very high density, high efficiency, low voltage, high current power modules were developed. A typical example features an isolated 3.3V/30A power module with a power density of 130W/in3 and an efficiency of 90% at 500 KHz switching frequency. / Ph. D.

Completed as a series of manuscripts, this dissertation reflects four aspects of my research into the intersections of conservation and sustainable development as practiced by conservation land trusts and community landcare groups, as well as by faculty and staff at land grant universities. The first paper included in this dissertation explores "Conservation 2.0" strategies being developed and employed by land trust across the US to integrate social and economic development goals into their conservation missions. The second paper explores one of these Conservation 2.0 strategies in greater detail, in particular the support of ecological entrepreneurship by land trusts and partners they involve in "ecological entrepreneurship support networks". The third piece emerged out of five years of engaged research with Catawba Landcare as one community landcare group in the region. As a means to capture the development path and history of the organization as well as to facilitate its path forward, I developed a dynamic content management system (CMS) based website for the group, which is explained in Chapter 4. The fourth and final piece of this dissertation is a collaboratively written piece that examines the relationship between Catawba Landcare and Virginia Tech using four theoretical lenses for community capacity building, ultimately proposing one engagement strategy for land grant universities to build and strengthen social infrastructure in their neighboring communities. In total, this collection of works chronicles a larger endeavor to explore place-based sustainability and the role of institutions and civil society in constructing a more sustainable future. / Ph. D.

Magnetoelectric (ME) materials are attracting increasing attention due to the achievable reading/writing source (electric field and magnetic field in most cases), fast response time, and larger storage density. Therefore, nanocomposites featuring both magnetostriction and piezoelectricity were investigated to increase the converse magnetoelectric (CME, α) coefficient. Among all the nanocomposites, vertically/horizontally-integrated heterostructures were investigated; these materials offer intimate lattice contact, lower clamping effect, dramatically enhanced α, easier reading direction, and the potential to be patterned for complicated applications. In the present work, we focused on three principal goals: (a) creating two-phase vertically integrated heterostructures with different ME materials that provide much larger α, and enhanced strain-induced magnetic shape anisotropy compared with the single-phased ME nanomaterials; (b) creating a vertically integrated heterostructure with large α, lower loss, and higher efficiency; and (c) investigating the stable magnetization states that this heterostructure could achieve, and how it can be used in advanced memory devices and logic devices. Firstly, a BiFeO3-CoFe2O4 (BFO-CFO) heterostructure was epitaxially deposited on Pb(Mg1/3Nb2/3) O3-x at%PbTiO3 (PMN-xPT). The resulting PMN-xPT was proven to have a large piezoelectric effect capable of boosting the CME in the heterostructure to create a much higher α. Secondly, a novel material, CuFe2O4 (CuFO), featuring lower coercivity and loss, was chosen to be self-assembled with BFO. This low-loss could increase the efficiency of the ME effect. Also, our findings revealed a much larger α in the vertically integrated heterostructure compared to single-layer CuFO. Accordingly, the self-assembled structure represents a convenient method for increasing the CME in multiferroic materials. Thirdly, the magnetization states for all these vertically integrated heterostructures were studied. Note that vertically integrated heterostructures are typically fabricated using materials with volatile properties. However, these composites have shown a non-volatile nature with a multi-states (N≥4), which is favored for multiple applications such as multi-level-cell. Moreover, several self-assembled heterostructures were created that are conducive to magnetic anisotropy/coercivity manipulation. One such example is Ni0.65Zn0.35Al0.8Fe1.2O4 (NZAFO) with BFO, which forms a self-assembled nanobelt heterostructure that exhibits high induced magnetic shape anisotropy, and is capable of manipulating magnetic coercivity (from 2 Oe to 50 Oe) and magnetic anisotropy directions (both in-plane and out-of-plane). Finally, we deposited a SrRuO3-CoFe2O4 (SRO-CFO) vertically integrated composite thin film on the single crystal substrate PMN-30PT, with a CFO nanopillar and SRO matrix. In such a heterostructure, the SRO would serve as the conductive materials, while CFO offers the insulated property. This unique conductive/insulating heterostructure could be deposited on PMN-PT single crystals, thus mimicking patterned electrodes on the PMN-PT single crystals with enhanced dielectric constant and 33. / Doctor of Philosophy / Multi-ferroic materials, which contain multiple ferroic orders like ferromagnetism/ferroelectricity order, were widely studied nowadays. These orders are coupled together, which could manipulate one order via another one through the coupling. Due to the achievable reading/writing source (electric field and magnetic field in most of the case), fast response time and larger storage density, magnetoelectric (ME) materials aroused most interests to-date. To be used in different applications, such as memory devices and logic devices, a high transfer efficiency, or say a high coupling coefficient, is required. However, single-phase materials have nearly neglectable ME effect. Therefore, a nanocomposite that contents both magnetostriction and piezoelectricity were investigated to increase the converse magnetoelectric (CME, α) coefficient. Amongst all the nanocomposite, a vertically integrated heterostructure was revealed, which has intimate lattice contact, lower clamping effect, dramatically enhancedα, easier reading direction, and potential to be patterned for complicated applications. In this present work, we focused on several different aspects: (a) creating two-phase vertically integrated heterostructure with different ME materials, which provides much larger α, large strain-induced magnetic shape anisotropy comparing with the single-phased ME nanomaterials; (b): creating a vertically integrated heterostructure with large α and lower losses and higher efficiency; (c) investigate the stable magnetization states that this heterostructure could achieve, which shows the potential of being used in advanced memory devices and logic devices. Firstly, in this work, a BiFeO3-CoFe2O4 (BFO-CFO) heterostructure was epitaxially deposited on the Pb(Mg1/3Nb2/3) O3-x at%PbTiO3 (PMN-xPT), which could boost the CME in the heterostructure to create a much higher α. Then, a novel materials CuFe2O4 (CuFO), was chosen to be self-assembled with BFO, which has lower losses and higher efficiency of the ME effect. Secondly, several self-assembled heterostructures were created, such as Ni0.65Zn0.35Al0.8Fe1.2O4 (NZAFO) with BFO, which manipulated the magnetic coercivity (from 2 Oe to 50 Oe) and magnetic anisotropy directions (Both in-plane and out-of-plane). And a heterostructure: SrRuO3 with CFO, created a vertically integrated heterostructure, could be used as patterned electrodes in different applications. Moreover, magnetization states were studied in all these vertically integrated heterostructures. A multi-states (N≥4) was revealed, which was favored by multiple applications such as multi-level-cell or logical devices. Finally, we deposited a SrRuO3-CoFe2O4 (SRO-CFO) vertically integrated composite thin film on the single crystal substrate PMN-30PT, with a CFO nanopillar and SRO matrix. In such a heterostructure, the SRO would serve as the conductive materials, while CFO offers the insulated property. This unique conductive/insulating heterostructure could be deposited on PMN-PT single crystals, thus mimicking patterned electrodes on the PMN-PT single crystals with enhanced dielectric constant and d_33.

No / The advance of high throughput biotechnology enables the generation of large amount of biomedical data. The microarray is increasingly a popular approach for the detection of genome-wide gene expression. Microarray data have thus increased significantly in public accessible database repositories, which provide valuable big data for scientific research. To deal with the challenge of microarray big data collected in different research labs using different experimental set-ups and on different bio-samples, this paper presents a primary study to evaluate the impact of two important factors (the origin of bio-samples and the quality of microarray data) on the integrated analytics of multiple microarray data. The aim is to enable the extraction of reliable and robust gene biomarkers from microarray big data. Our work showed that in order to enhance biomarker discovery from microarray big data (i) it is necessary to treat the microarray data differently in terms of their quality, (ii) it is recommended to stratifying (i.e., sub-group) the data according to the origin of bio-samples in the analytics.

Most current commercial automated IC inspection systems use gray-level or binary images for IC defect detection in spite of the fact that color permits defect detection where gray-level information is insufficient. Three color image processing techniques including the spectral-spatial clustering, principal components, and hue-saturation-value (HSV) color features have been investigated to evaluate the usefulness of color for IC defect detection. The AMOEBA spectral-spatial clustering algorithm, an un-supervised color segmentation approach, with a sequence of image processing procedures resulted in segmentation results with high accuracy and discriminated successfully an isolated and homogeneous defect with an unique color signature. The principal components transformation and the HSV color features, two color enhancement/separation algorithms, have proven useful for enhancing and isolating weak spectral signatures in the defect regions. The results of this investigation into the use of color are promising.

This paper discusses an intelligence driven test system for generation of test sequences for stuck-open faults in CMOS VLSI sequential circuits. The networks in system evaluation are compiled from an RTL representation of the digital system. To excite a stuck-open fault it is only necessary that the output of the gate containing the fault take on opposite values during two successive clock periods. Excitation of the fault must therefore constrain two successive input/present-state vectors, referred to in the paper as the pregoal and goal nodes respectively. An initialization procedure is used to determine the pregoal state. Two theorems are proved establishing a 1-1 correspondence between stuck-at and stuck-open faults. As a result the D-algorithm may be used to determine the goal node. Determining the nodes was tried on many circuits and a high success rate was achieved. The pregoal is observed to have more "don't care" values. The next step is a "sensitization search" for an input sequence (X(s)) that drives the memory elements to the determined pregoal and goal states over two consecutive clock periods. It is easier for the search to reach the pregoal due to the greater number of "don't cares." Following a "propagation search" for an input sequence (X(p)) to drive the effect of the fault to an external output, the sequence of vectors (X(s)), (X(p)) will be passed to an "ALL-Fault Simulator" for verification. The simulation will be clock mode but will represent the output retention resulting from the stuck-open faults. One measure of the value of a special search procedure for stuck-open faults can be obtained by comparing the results employing this search with results obtained by searching only for the analogous stuck-at faults. A first order prediction would be a likelihood less than 0.5 that the predecessor of a stuck-at goal node would excite an opposite output in the gate containing the fault. A comparison of the two methods using the stuck-open "All-Fault Simulator" is presented.

This dissertation describes a new simulation technique for an automatic test generation system, SCIRTSS version 4.0 (Sequential Circuit Test Sequence System). This test generation system is driven by the hardware compiler AHPL, a Hardware Programming Language, and an intelligent heuristic-based search for test vector generation. Using a fault-injection gate-level simulator and the generated test vector, all the faulty states of the circuit are simulated in parallel and the simulator is thus able to find all detected faults by a particular input sequence. The major objective of this research was to develop a faster replacement for the existing simulation process. The philosophy of divide and conquer is used in the development of the new simulation technique. Sequential networks are divided into combinational sub-networks, and, if necessary, the combinational sub-networks are further reduced into fan-out free regions. Thus, the problem is reduced to a relatively simple combinational one. In addition to the classical faults, the new simulator attempts to detect CMOS stuck-open faults. Several circuits were tested under SCIRTSS 4.0 using both the existing and the new simulation techniques. The results are listed in this paper to verify superiority of the new simulation technique.

For the congestion issue, we found that the existing congestion models will very often over-estimate the congestion at the densely routed regions because real routers will perform rip-up and re-route operations and route the nets with detour to avoid overflow. We propose a 3-step approach that is designed to tackle this problem. It can simulate the global routing, detailed routing and rip-up and re-route process in the real routing procedure. Results show that the prediction accuracy can be improved by 30%. In addition, we have also implemented a routability-driven floorplanner with our congestion model. Results show that the number of un-routable wires can be reduced if the number of overflow tiles can be reduced during floorplanning. Then we studied and developed two post-processing steps to be applied on an interconnect optimized floorplan or placement to further reduce the total wirelength or area. For the wirelength issue, we presented an elegant solution to the cell flipping problem. We presented a detailed study of this cell flipping problem in a placement result to reduce interconnect length. We find the optimal flipping of the cells by formulating the cell flipping problem as a mixed integer linear programming problem to give the shortest total wirelength. In order to reduce the runtime, we proposed a cell orientation fixing step to fix the orientations of some cells. Results show that we can obtain optimal result by solving the mixed integer linear programming problem of the remaining variables directly or the problem can be solved by linear programming such that we can still obtain a result very close to the optimal solution with a much shorter runtime. For area reduction on an interconnect optimized floorplan, we proposed a new approach called deadspace utilization to reduce the total area of an interconnect optimized floorplan by making use of the shape flexibility of some modules. Results show that we can apply this deadspace utilization technique to reduce the area and wirelength of the original floorplan further, subject to the constraint of maintaining the routability and congestion of the original floorplan. / We have studied several interconnect-related optimization problems in floor-planning and placement of VLSI circuits in details. When the number of small logic gates is large in a circuit design, good netlist designs may still result in poor layouts because of various interconnect problems. Most of the problems cannot be fixed manually today because of the incomprehensible circuit complexity. Design automation techniques on interconnect issues in physical design of VLSI circuits becomes indispensable. Recently, congestion minimization and wirelength optimization are two hot topics in interconnect planning. / Sham Chiu Wing. / "March 2006." / Adviser: Young Fung Yu. / Source: Dissertation Abstracts International, Volume: 67-11, Section: B, page: 6634. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references (p. 106-115). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

Lai Tsz Wai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 123-129). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- VLSI Design Cycle --- p.2 / Chapter 1.2 --- Physical Design Cycle --- p.4 / Chapter 1.3 --- Floorplanning --- p.7 / Chapter 1.3.1 --- Types of Floorplan and Floorplan Representations --- p.11 / Chapter 1.3.2 --- Interconnect-driven Floorplanning --- p.13 / Chapter 1.4 --- Motivations and Contributions --- p.17 / Chapter 1.5 --- Organization of this Thesis --- p.18 / Chapter 2 --- Literature Review on Floorplan Representation --- p.20 / Chapter 2.1 --- Slicing Floorplan Representation --- p.20 / Chapter 2.1.1 --- Normalized Polish Expression --- p.20 / Chapter 2.2 --- Non-slicing Floorplan Representations --- p.21 / Chapter 2.2.1 --- Sequence Pair (SP) --- p.21 / Chapter 2.2.2 --- Bounded-sliceline Grid (BSG) --- p.23 / Chapter 2.2.3 --- O-tree --- p.25 / Chapter 2.2.4 --- B*-tree --- p.26 / Chapter 2.3 --- Mosaic Floorplan Representations --- p.28 / Chapter 2.3.1 --- Corner Block List (CBL) --- p.28 / Chapter 2.3.2 --- Twin Binary Trees (TBT) --- p.31 / Chapter 2.3.3 --- Twin Binary Sequences (TBS) --- p.32 / Chapter 2.4 --- Summary --- p.34 / Chapter 3 --- Literature Review on Interconnect Optimization in Floorplan- ning --- p.37 / Chapter 3.1 --- Wirelength Estimation --- p.37 / Chapter 3.2 --- Congestion Optimization --- p.38 / Chapter 3.2.1 --- Integrated Floorplanning and Interconnect Planning --- p.41 / Chapter 3.2.2 --- Multi-layer Global Wiring Planning (GWP) --- p.43 / Chapter 3.2.3 --- Estimating Routing Congestion using Probabilistic Anal- ysis --- p.44 / Chapter 3.2.4 --- Congestion Minimization During Placement --- p.46 / Chapter 3.2.5 --- Modelling and Minimization of Routing Congestion --- p.48 / Chapter 3.3 --- Buffer Planning --- p.49 / Chapter 3.3.1 --- Buffer Clustering with Feasible Region --- p.51 / Chapter 3.3.2 --- Routability-driven Repeater Clustering Algorithm with Iterative Deletion --- p.55 / Chapter 3.3.3 --- Planning Buffer Locations by Network Flow --- p.58 / Chapter 3.3.4 --- Buffer Planning using Integer Multicommodity Flow --- p.60 / Chapter 3.3.5 --- Buffer Planning Problem using Tile Graph --- p.60 / Chapter 3.3.6 --- Probabilistic Analysis for Buffer Block Planning --- p.62 / Chapter 3.3.7 --- Fast Buffer Planning and Congestion Optimization --- p.63 / Chapter 3.4 --- Summary --- p.66 / Chapter 4 --- Congestion Evaluation: Wire Density Model --- p.68 / Chapter 4.1 --- Introduction --- p.68 / Chapter 4.2 --- Overview of Our Floorplanner --- p.70 / Chapter 4.3 --- Wire Density Model --- p.71 / Chapter 4.3.1 --- Computation of Ni --- p.72 / Chapter 4.3.2 --- Computation of Pi --- p.74 / Chapter 4.3.3 --- Usage of Mirror TBT --- p.76 / Chapter 4.4 --- Implementation --- p.76 / Chapter 4.4.1 --- Efficient Calculation of Ni --- p.76 / Chapter 4.4.2 --- Solving the LCA Problem Efficiently --- p.81 / Chapter 4.4.3 --- Cost Function --- p.81 / Chapter 4.4.4 --- Complexity --- p.81 / Chapter 4.5 --- Experimental Results --- p.82 / Chapter 4.6 --- Conclusion --- p.83 / Chapter 5 --- Buffer Planning: Simple Buffer Planning Method --- p.85 / Chapter 5.1 --- Introduction --- p.85 / Chapter 5.2 --- Variable Interval Buffer Insertion Constraint --- p.87 / Chapter 5.3 --- Overview of Our Floorplanner --- p.88 / Chapter 5.4 --- Buffer Planning --- p.89 / Chapter 5.4.1 --- Feasible Grids --- p.89 / Chapter 5.4.2 --- Table Look-up Approach --- p.89 / Chapter 5.5 --- Implementation --- p.91 / Chapter 5.5.1 --- Building the Look-up Tables --- p.91 / Chapter 5.5.2 --- An Example of Look-up Table Construction --- p.94 / Chapter 5.5.3 --- A Faster Approach for Building the Look-up Tables --- p.101 / Chapter 5.5.4 --- An Example of the Faster Look-up Table Construction --- p.105 / Chapter 5.5.5 --- I/O Pin Locations --- p.106 / Chapter 5.5.6 --- Cost Function --- p.110 / Chapter 5.5.7 --- Complexity --- p.111 / Chapter 5.6 --- Experimental Results --- p.112 / Chapter 5.6.1 --- Selected Value for A --- p.112 / Chapter 5.6.2 --- Performance of Our Floorplanner --- p.113 / Chapter 5.7 --- Conclusion --- p.116 / Chapter 6 --- Conclusion --- p.118 / Chapter A --- An Efficient Algorithm for the Least Common Ancestor Prob- lem --- p.120 / Bibliography --- p.123