No description available.

Thesis (M. S.)--Chemical Engineering, Georgia Institute of Technology, 2009. / Committee Chair: Kohl, Paul; Committee Member: Bidstrup Allen, Sue Ann; Committee Member: Fuller, Thomas; Committee Member: Hesketh, Peter; Committee Member: Hess, Dennis; Committee Member: Meindl, James.

No description available.

The adaptation of standard integrated circuit (IC) technology for biosensors in drug discovery pharmacology, neural interface systems, environmental sensors and electrophysiology requires electrodes to be electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous IC technology, complementary metal oxide semiconductor (CMOS), does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved by others. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. The scope of this work was to develop post-processing methods that meet the electrochemical and biocompatibility requirements but within the low-cost constraint. Several approaches were appraised with the two most promising designs taken forward for further investigation. Firstly, a process was developed whereby the corrodible aluminium is anodised to form nanoporous alumina and further processed to optimise its impedance. A second design included a noble metal in the alumina pores to enhance further the electrical characteristics of the electrode. Experiments demonstrated for the first time the ability to anodise CMOS metallisation to form the desired electrodes. Tests showed the electrode addressed the problems of corrosion and presented a surface that was biocompatible with the NG108-15 neuronal cell line. Difficulties in assessing the influence of alumina porosity led to the development of a novel cell adhesion assay that showed for the first time neuronal cells adhere preferentially to large pores rather than small pores or planar aluminium. It was also demonstrated that porosity can be manipulated at room temperature by modifying the anodising electrolyte with polyethylene glycol. CMOS ICs were designed as multiple electrode arrays and optimised for neuronal recordings. This utilised the design incorporating a noble metal deposited into the porous alumina. Deposition of platinum was only partially successful, with better results using gold. This provided an electrode surface suitable for electric cell-substrate impedance sensors (ECIS) and many other sensor applications. Further processing deposited platinum black to improve signal-to-noise ratio for neuronal recordings. The developed processes require no specialised semiconductor fabrication equipment and can process CMOS ICs on laboratory or factory bench tops in less than one hour. During the course of electrode development, new methods for biosensor packaging were assessed: firstly, a biocompatible polyethylene glycol mould process was developed for improved prototype assembly. Secondly, a commercial ‘partial encapsulation’ process (Quik-Pak, U.S.) was assessed for biocompatibility. Cell vitality tests showed both methods were biocompatible and therefore suitable for use in cell-based biosensors. The post-processed CMOS electrode arrays were demonstrated by successfully recording neuronal cell electrical activity (action potentials) and by ECIS with a human epithelial cell line (Caco2). It is evident that these developments may provide a missing link that can enable commercialisation of CMOS biosensors. Further work is being planned to demonstrate the technology in context for specific markets.

<p>Today’s microprocessors with millions of transistors perform high-complexity computing at multi-gigahertz clock frequencies. The ever-increasing chip size and speed call for new methodologies in clock distribution network. Conventional global synchronization techniques exhibit many drawbacks in the advanced VLSI chips such as high-speed microprocessors. A significant percentage of the total power consumption in a microprocessor is dissipated in the clock distribution network. Also since the chip dimensions increase, clock skew management becomes very challenging in the framework of conventional methodology. Long interconnect delays limit the maximum clock frequency and become a bottleneck for future microprocessor design. In such a situation, new alternative techniques for synchronization in system-on-chip are demanded.</p><p>This thesis presents new alternatives for traditional clocking and synchronization methods, in which, speed and power consumption bottlenecks are treated. For this purpose, two new techniques based on mesochronous synchronization and resonant clocking are investigated. The mesochronous synchronization technique deals with remedies for skew and delay management. Using this technique, clock frequency up to 5 GHz for on-chip communication is achievable in 0.18-<em>μ</em>m CMOS process. On the other hand the resonant clocking solves significant power dissipation problem in the clock network. This method shows a great potential in power saving in very large-scale integrated circuits. According to measurements, 2.3X power saving in clock distribution network is achieved in 130-nm CMOS process. In the resonant clocking, oscillator plays a crucial role as a clock generator. Therefore an investigation about oscillators and possible techniques for jitter and phase noise reduction in clock generators has been done in this research framework. For this purpose a study of injection locking phenomenon in ring oscillators is presented. This phenomenon can be used as a jitter suppression mechanism in the oscillators. Also a new implementation of the DLL-based clock generators using ring oscillators is presented in 130-nm CMOS process. The measurements show that this structure operates in the frequency range of 100 MHz-1.5 GHz, and consumes less power and area compared to the previously reported structures. Finally a new implementation of a 1.8-GHz quadrature oscillator with wide tuning range is presented. The quadrature oscillators potentially can be used as future clock generators where multi-phase clock is needed.</p> / Report code: LiU-TEK-LIC-2006:22

­^¤åºK­n¡G In this thesis, a two-step de-embedded techniques was applied to measure the important parameters, ft and fmax , of the heterojunction bipolar transistors(HBTs). The same technique was also used to measure the wide-band S parameters for modeling and evaluating the bump chip carrier(BCC) packages. In the simulation, the Ansoft HFSS simulator was used to calculate the insertion and return losses for some bare and packaged test chips. Comparison between simulated and measured results has been discussed in detail to illustrate the applicability of the HFSS simulator.

Thesis (M.S.)--Oregon State University, 2010. / Printout. Includes bibliographical references (leaves 97-106). Also available on the World Wide Web.

Thesis (Ph. D.)--School of Electrical and Computer Engineering, Georgia Institute of Technology, 2004. Directed by James D. Meindl. / Vita. Includes bibliographical references (leaves 289-297).

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009. / Committee Chair: Madhavan Swaminathan; Committee Member: Andrew E. Peterson; Committee Member: Emmanouil M. Tentzeris; Committee Member: Hao-Min Zhou; Committee Member: Saibal Mukhopadhyay. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Not available / text