Fault-tolerance, which is a complement to fault prevention, is an effective method of achieving ultra-high reliability. By taking this approach fault free computation can be achieved despite the presence of fault in the system. In this thesis three new fault tolerant techniques are presented and their advantages over well known fault-tolerant strategies are shown. One of these new techniques achieves higher reliability than any other similar techniques presented in the literature. Generally fault-tolerant structures consist of four major blocks: the replicated modules, the disagreement and detection circuit, the switching circuit, and the voting mechanism. The most critical component in a fault-tolerant system is the voter because the final output of the system is computed by this component. This dissertation presents a new implementation for voters which reduces both the complexity and the occupied area on the chip. The structures of the three techniques developed in this work are such that the complexity of their switching mechanisms grows only linearly with the number of modules but the voting mechanism complexity increases significantly. This is a better approach than those schemes in which the switching complexity increases significantly and the voter's complexity remains constant or grows linearly with the number of modules because it is easier to implement a complex voter than a complex switch (voters have more regular structures). Extensive comparisons are made between different fault-tolerant techniques. A new reliability model is also developed for system reliability evaluation of the new designs. The results of these analyses are plotted, and the advantages of the new techniques are demonstrated. In the final part of the work an expert system is described which uses the knowledge acquired by these comparisons. This expert system is meant as a prototype of a component of a CAD tool which will act as an advisor on fault-tolerant techniques.

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Thesis (M.S.)--Materials Science and Engineering, Georgia Institute of Technology, 2005. / Suresh, Committee Member ; C.P. Wong, Committee Member ; Rao R. Tummala, Committee Chair. Includes bibliographical references.

Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.

This dissertation explores the cost of programmability in computing devices as measured relative to fixed-function devices implementing the same functionality using the same physical fabrication technology. The central claim elevates programmability to an explicit design parameter that (1) can be rigorously defined, (2) has measurable costs amenable to high-level modeling, (3) yields a design-space with distinct regions and properties, and (4) can be usefully manipulated using computer-aided design tools. The first portion of the the work is devoted to laying a rigorous logical foundation to support both this and future work on the subject. The second portion supports the thesis within this established logical foundation, using a specific engineering problem as a narrative vehicle. The engineering problem explored is that of mechanically adding a useful degree of programmability into preexisting fixed-function logic while minimizing the added overhead. Varying criteria for usefulness are proposed and the relative costs estimated both analytically and through case-study using standard-cell logic synthesis. In the case study, a methodology for the automatic generation of reconfigurable logic highly optimized for a specific set of computing applications is demonstrated. The approach stands in contrast to traditional reconfigurable computing techniques which focus on providing general purpose functionality at the expense of substantial overheads relative to fixed-purpose implementations. / text

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This thesis presents two experimental microelectronic prototypes for neurophysiological applications. Both systems target diagnostics and treatment of neurological disorders, and they are experimentally validated in vivo by online intracranial EEG recording in freely moving rats. The first prototype is a 56-channel chopper-stabilized low-noise neural recording interface IC with programmable mixed-signal DC cancellation feedback, fabricated in a 0.13μm CMOS process. Each recording channel has a low-noise fully-differential amplifier, and a digital integrator and a delta-sigma DAC in the feedback to cancel DC offsets of up to ±50mV. Chopper stabilization technique is used to reduce the amplifier flicker noise. The recorded signals are digitized by 7 column-parallel SAR ADCs. The second prototype is a compact headset for multi-site neuromonitoring and neurostimulation in rodent brain. A stack of 2 mini-PCBs was designed and experimentally validated. It includes a previously fabricated 0.35μm CMOS recording and stimulation IC, a low-power FPGA, and the IC peripherals.

This thesis presents two experimental microelectronic prototypes for neurophysiological applications. Both systems target diagnostics and treatment of neurological disorders, and they are experimentally validated in vivo by online intracranial EEG recording in freely moving rats. The first prototype is a 56-channel chopper-stabilized low-noise neural recording interface IC with programmable mixed-signal DC cancellation feedback, fabricated in a 0.13μm CMOS process. Each recording channel has a low-noise fully-differential amplifier, and a digital integrator and a delta-sigma DAC in the feedback to cancel DC offsets of up to ±50mV. Chopper stabilization technique is used to reduce the amplifier flicker noise. The recorded signals are digitized by 7 column-parallel SAR ADCs. The second prototype is a compact headset for multi-site neuromonitoring and neurostimulation in rodent brain. A stack of 2 mini-PCBs was designed and experimentally validated. It includes a previously fabricated 0.35μm CMOS recording and stimulation IC, a low-power FPGA, and the IC peripherals.