The dramatic increase in market demand for wireless products has inspired a trend for new designs. These designs are smaller, less expensive, and consume less power. A natural result of this trend has been the push for components that are more highly integrated and take up less real estate on the printed circuit board (PCB). Major efforts are underway to reduce the number of integrated circuits (ICs) in newer designs by incorporating several functions into a single chip. Availability of newer technologies such as silicon bipolar with complementary metal oxide semiconductor (BiCMOS) has helped facilitate this move toward more complex circuit topologies onto one die. BiCMOS achieves efficient chip area utilization by combining bipolar transistors, suited for higher frequency analog circuits with CMOS transistors that are useful for digital functions and lower frequency analog circuits. A voltage controlled oscillator (VCO) is just one radio frequency (RF) circuit block that can benefit from a more complex semiconductor process like BiCMOS. This thesis presents the design and evaluation of an integrated VCO in the IBM 5S BiCMOS process. IBM 5S is a 0.5 um, single poly, five-metal process with surface channel PFETs and NFETs. The process also features self-aligned extrinsic base NPN bipolar devices exhibiting ft of up to 24 GHz. The objective of this work is to obtain a VCO design that provides a high degree of functionality while maximizing performance over environmental conditions. It is shown that an external feedback and resonator network as well as a bandgap voltage referenced bias circuit help to achieve these goals. An additional objective for this work is to highlight several pragmatic issues associated with designing an integrated VCO capable of high volume production. The Clapp variant of the Colpitts topology is selected for this application for reasons of robust operation, frequency stability, and ease of implementing in integrated form. Design is performed at 560 MHz using the negative resistance concept. Simulation results from Pspice and the Agilent ADS are presented. Implementation related issues such as bondwire inductances and layout details are covered. The VCO characterization is shown over several environmental conditions. The final nominal design is capable of: tuning over 150 MHz (22%) and delivering â 4.2 dBm into a 50 Ohm load while consuming only 9mA from a 3.0V supply. The phase noise at these conditions is -92.5 dBc/Hz at a frequency offset of 10 kHz from the carrier. Finally, the conclusion of this work lists some suggestions for potential future research. / Master of Science

A novel method for modeling bends in coplanar waveguides (CPWs) is described. The CPW can be viewed as a pair of parallel coupled quasi-slot lines. Bends in the CPW are modeled as a non-uniform coupled line system in terms of their even- and odd- mode characteristics. This modeling approach is general and can be applied for bends with different angles and other similar discontinuities in the CPW. The salient feature of the model is the simplified illustration of frequency dependent effects in the bend. Right-angle, 45 degree, and mitered right-angle bends in the CPW are analyzed, and models are developed for each bend structure. The procedure for extracting the modal scattering matrix from the model is presented. To demonstrate the accuracy of the model, modal transmission coefficients obtained from the model are compared with full-wave electromagnetic simulations. Good agreement between the model and full-wave simulation results over a wide frequency range is demonstrated. The transfer of energy between even and odd modes in the bend is investigated and the effect of the physical properties of the CPW on mode conversion is analyzed in detail. Mode conversion at discontinuities like the bend in CPWs cause non-ideal behavior in the two-port (even-mode) measurements of such circuits. Theoretical prediction of the measured response is discussed along with the predicted response for transmission coefficient from model and full-wave simulations. Comparison between the measurements of a right-angle bend and the corresponding model results shows good agreement. Implementation of the model in SPICE is also discussed. / Graduation date: 2004

No description available.

This work deals with verification possibilities of integrated circuits, especially with hardware emulation. The first part of the text briefly describes designing process of an integrated circuit, which includes emulation using emulation platforms. The main part of this work deals with the innovation of the emulation platform, which is used by SCG Czech Design Center s. r. o. Possible ways to improve the current emulation platform are explored and further taken into account when designing a universal emulation platform. Last part of this work deals with functional verification of the proposed universal emulation platform. Functionality will be verified by emulation of the basic control functions of the NCP1246 circuit.

No description available.

No description available.

Tan Xuesong. / "June 2004." / Thesis (Ph.D.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (p. 247-251). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

For the congestion issue, we found that the existing congestion models will very often over-estimate the congestion at the densely routed regions because real routers will perform rip-up and re-route operations and route the nets with detour to avoid overflow. We propose a 3-step approach that is designed to tackle this problem. It can simulate the global routing, detailed routing and rip-up and re-route process in the real routing procedure. Results show that the prediction accuracy can be improved by 30%. In addition, we have also implemented a routability-driven floorplanner with our congestion model. Results show that the number of un-routable wires can be reduced if the number of overflow tiles can be reduced during floorplanning. Then we studied and developed two post-processing steps to be applied on an interconnect optimized floorplan or placement to further reduce the total wirelength or area. For the wirelength issue, we presented an elegant solution to the cell flipping problem. We presented a detailed study of this cell flipping problem in a placement result to reduce interconnect length. We find the optimal flipping of the cells by formulating the cell flipping problem as a mixed integer linear programming problem to give the shortest total wirelength. In order to reduce the runtime, we proposed a cell orientation fixing step to fix the orientations of some cells. Results show that we can obtain optimal result by solving the mixed integer linear programming problem of the remaining variables directly or the problem can be solved by linear programming such that we can still obtain a result very close to the optimal solution with a much shorter runtime. For area reduction on an interconnect optimized floorplan, we proposed a new approach called deadspace utilization to reduce the total area of an interconnect optimized floorplan by making use of the shape flexibility of some modules. Results show that we can apply this deadspace utilization technique to reduce the area and wirelength of the original floorplan further, subject to the constraint of maintaining the routability and congestion of the original floorplan. / We have studied several interconnect-related optimization problems in floor-planning and placement of VLSI circuits in details. When the number of small logic gates is large in a circuit design, good netlist designs may still result in poor layouts because of various interconnect problems. Most of the problems cannot be fixed manually today because of the incomprehensible circuit complexity. Design automation techniques on interconnect issues in physical design of VLSI circuits becomes indispensable. Recently, congestion minimization and wirelength optimization are two hot topics in interconnect planning. / Sham Chiu Wing. / "March 2006." / Adviser: Young Fung Yu. / Source: Dissertation Abstracts International, Volume: 67-11, Section: B, page: 6634. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references (p. 106-115). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

Lai Tsz Wai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 123-129). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- VLSI Design Cycle --- p.2 / Chapter 1.2 --- Physical Design Cycle --- p.4 / Chapter 1.3 --- Floorplanning --- p.7 / Chapter 1.3.1 --- Types of Floorplan and Floorplan Representations --- p.11 / Chapter 1.3.2 --- Interconnect-driven Floorplanning --- p.13 / Chapter 1.4 --- Motivations and Contributions --- p.17 / Chapter 1.5 --- Organization of this Thesis --- p.18 / Chapter 2 --- Literature Review on Floorplan Representation --- p.20 / Chapter 2.1 --- Slicing Floorplan Representation --- p.20 / Chapter 2.1.1 --- Normalized Polish Expression --- p.20 / Chapter 2.2 --- Non-slicing Floorplan Representations --- p.21 / Chapter 2.2.1 --- Sequence Pair (SP) --- p.21 / Chapter 2.2.2 --- Bounded-sliceline Grid (BSG) --- p.23 / Chapter 2.2.3 --- O-tree --- p.25 / Chapter 2.2.4 --- B*-tree --- p.26 / Chapter 2.3 --- Mosaic Floorplan Representations --- p.28 / Chapter 2.3.1 --- Corner Block List (CBL) --- p.28 / Chapter 2.3.2 --- Twin Binary Trees (TBT) --- p.31 / Chapter 2.3.3 --- Twin Binary Sequences (TBS) --- p.32 / Chapter 2.4 --- Summary --- p.34 / Chapter 3 --- Literature Review on Interconnect Optimization in Floorplan- ning --- p.37 / Chapter 3.1 --- Wirelength Estimation --- p.37 / Chapter 3.2 --- Congestion Optimization --- p.38 / Chapter 3.2.1 --- Integrated Floorplanning and Interconnect Planning --- p.41 / Chapter 3.2.2 --- Multi-layer Global Wiring Planning (GWP) --- p.43 / Chapter 3.2.3 --- Estimating Routing Congestion using Probabilistic Anal- ysis --- p.44 / Chapter 3.2.4 --- Congestion Minimization During Placement --- p.46 / Chapter 3.2.5 --- Modelling and Minimization of Routing Congestion --- p.48 / Chapter 3.3 --- Buffer Planning --- p.49 / Chapter 3.3.1 --- Buffer Clustering with Feasible Region --- p.51 / Chapter 3.3.2 --- Routability-driven Repeater Clustering Algorithm with Iterative Deletion --- p.55 / Chapter 3.3.3 --- Planning Buffer Locations by Network Flow --- p.58 / Chapter 3.3.4 --- Buffer Planning using Integer Multicommodity Flow --- p.60 / Chapter 3.3.5 --- Buffer Planning Problem using Tile Graph --- p.60 / Chapter 3.3.6 --- Probabilistic Analysis for Buffer Block Planning --- p.62 / Chapter 3.3.7 --- Fast Buffer Planning and Congestion Optimization --- p.63 / Chapter 3.4 --- Summary --- p.66 / Chapter 4 --- Congestion Evaluation: Wire Density Model --- p.68 / Chapter 4.1 --- Introduction --- p.68 / Chapter 4.2 --- Overview of Our Floorplanner --- p.70 / Chapter 4.3 --- Wire Density Model --- p.71 / Chapter 4.3.1 --- Computation of Ni --- p.72 / Chapter 4.3.2 --- Computation of Pi --- p.74 / Chapter 4.3.3 --- Usage of Mirror TBT --- p.76 / Chapter 4.4 --- Implementation --- p.76 / Chapter 4.4.1 --- Efficient Calculation of Ni --- p.76 / Chapter 4.4.2 --- Solving the LCA Problem Efficiently --- p.81 / Chapter 4.4.3 --- Cost Function --- p.81 / Chapter 4.4.4 --- Complexity --- p.81 / Chapter 4.5 --- Experimental Results --- p.82 / Chapter 4.6 --- Conclusion --- p.83 / Chapter 5 --- Buffer Planning: Simple Buffer Planning Method --- p.85 / Chapter 5.1 --- Introduction --- p.85 / Chapter 5.2 --- Variable Interval Buffer Insertion Constraint --- p.87 / Chapter 5.3 --- Overview of Our Floorplanner --- p.88 / Chapter 5.4 --- Buffer Planning --- p.89 / Chapter 5.4.1 --- Feasible Grids --- p.89 / Chapter 5.4.2 --- Table Look-up Approach --- p.89 / Chapter 5.5 --- Implementation --- p.91 / Chapter 5.5.1 --- Building the Look-up Tables --- p.91 / Chapter 5.5.2 --- An Example of Look-up Table Construction --- p.94 / Chapter 5.5.3 --- A Faster Approach for Building the Look-up Tables --- p.101 / Chapter 5.5.4 --- An Example of the Faster Look-up Table Construction --- p.105 / Chapter 5.5.5 --- I/O Pin Locations --- p.106 / Chapter 5.5.6 --- Cost Function --- p.110 / Chapter 5.5.7 --- Complexity --- p.111 / Chapter 5.6 --- Experimental Results --- p.112 / Chapter 5.6.1 --- Selected Value for A --- p.112 / Chapter 5.6.2 --- Performance of Our Floorplanner --- p.113 / Chapter 5.7 --- Conclusion --- p.116 / Chapter 6 --- Conclusion --- p.118 / Chapter A --- An Efficient Algorithm for the Least Common Ancestor Prob- lem --- p.120 / Bibliography --- p.123

Ma, Tilen. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (leaves 98-100). / Abstracts in English and Chinese. / Abstract --- p.i / Chapter 0.1 --- Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Physical Design Cycle --- p.2 / Chapter 1.2 --- Floorplanning --- p.6 / Chapter 1.2.1 --- Floorplanning Objectives --- p.7 / Chapter 1.2.2 --- Common Approaches --- p.8 / Chapter 1.3 --- Motivations and Contributions --- p.11 / Chapter 1.4 --- Organization of the Thesis --- p.13 / Chapter 2 --- Literature Review on Placement Constraints in Floorplanning --- p.15 / Chapter 2.1 --- Introduction --- p.15 / Chapter 2.2 --- Algorithms for Abutment Constraint --- p.16 / Chapter 2.3 --- Algorithms for Alignment Constraint --- p.18 / Chapter 2.4 --- Algorithms for Boundary Constraint --- p.20 / Chapter 2.5 --- Unified Approach for Placement Constraints --- p.23 / Chapter 2.5.1 --- Representation of Placement Constraints --- p.23 / Chapter 2.5.2 --- Handling Relative Placement Constraints --- p.24 / Chapter 2.5.3 --- Examples for Handling Placement Constraints --- p.25 / Chapter 3 --- Literature Review on Bus-Driven Floorplanning --- p.28 / Chapter 3.1 --- Introduction --- p.28 / Chapter 3.2 --- Previous Work --- p.28 / Chapter 3.2.1 --- Zero-Bend Bus-Driven Floorplanning [3] --- p.28 / Chapter 3.2.2 --- Two-Bend Bus-Driven Floorplanning [1] --- p.32 / Chapter 4 --- Placement Constraints for Multi-Bend Bus in TCGs --- p.38 / Chapter 4.1 --- Introduction --- p.38 / Chapter 4.2 --- Transitive Closure Graph [6] --- p.39 / Chapter 4.3 --- Placement Constraints for Zero-Bend Bus --- p.41 / Chapter 4.4 --- Placement Constraints for Multi-Bend Bus --- p.44 / Chapter 4.5 --- Placement Constraints for Bus Ordering --- p.45 / Chapter 4.5.1 --- Natural Bus Ordering in TCGs --- p.45 / Chapter 4.5.2 --- Explicit Bus Ordering in TCGs --- p.46 / Chapter 5 --- TCG-Based Bus-Driven Floorplanning --- p.48 / Chapter 5.1 --- Motivation --- p.48 / Chapter 5.2 --- Problem Formulation --- p.49 / Chapter 5.3 --- Methodology --- p.50 / Chapter 5.3.1 --- Construction of Reduced Graphs --- p.51 / Chapter 5.3.2 --- Construction of Common Graph --- p.52 / Chapter 5.3.3 --- Spanning Tree for Bus Assignment --- p.53 / Chapter 5.3.4 --- Formation of Bus Components --- p.55 / Chapter 5.3.5 --- Bus Feasibility Check --- p.56 / Chapter 5.3.6 --- Overlap Removal --- p.57 / Chapter 5.3.7 --- Floorplan Realization --- p.58 / Chapter 5.3.8 --- Simulated Annealing --- p.58 / Chapter 5.3.9 --- Soft Module Adjustment --- p.60 / Chapter 5.4 --- Experimental Results --- p.60 / Chapter 5.5 --- Summary --- p.65 / Chapter 6 --- Conclusion --- p.67 / Chapter A --- Appendix --- p.69 / Chapter A.1 --- Well-Known Algorithms --- p.69 / Chapter A.1.1 --- Kruskal's Algorithm --- p.69 / Chapter A.1.2 --- Bellman-Ford Algorithm --- p.69 / Chapter A.2 --- Figures of Resulting Floorplans --- p.71 / Chapter A.2.1 --- Data Set One --- p.71 / Chapter A.2.2 --- Data Set Two --- p.80 / Chapter A.2.3 --- Data Set Three --- p.85 / Chapter A.2.4 --- Data Set Four --- p.92 / Bibliography --- p.98