Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2005. / Includes bibliographical references (leaves 134-141). Also available in electronic version.

Thesis (Ph. D.)--University of Texas at Austin, 2005. / Vita. Includes bibliographical references.

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

Thesis (M.S.)--Oregon State University, 2008. / Printout. Includes bibliographical references (leaves 80-84). Also available on the World Wide Web.

Thesis (Ph. D.)--Washington State University, August 2007. / Includes bibliographical references (p. 89-97).

Orientador: Jose Antonio Siqueira Dias / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-09T20:31:51Z (GMT). No. of bitstreams: 1 Tozetto_EduardoHenrique_M.pdf: 2634313 bytes, checksum: 16d70c7f88dab18e657af6ec34a2defb (MD5) Previous issue date: 2007 / Resumo: O contexto econômico competitivo em que as empresas que desenvolvem ferramentas para projeto de CIs estão inseridas dificulta o estabelecimento de padrões e plataformas de desenvolvimento comuns. Em geral, a necessidade de inúmeras ferramentas resulta em um ambiente de projeto fragmentado. Este trabalho apresenta uma ferramenta desenvolvida através da implementação de interfaces gráficas paramétricas em TCL/TK, que integra funções gerais, permitindo a rápida codificação de procedimentos e seu acesso através de elementos gráficos. A ferramenta desenvolvida serve para facilitar e otimizar as tarefas envolvidas no aprimoramento das técnicas de projeto de Circuitos ntegrados através da elaboração de métodos e scripts visando à automação de etapas do fluxo de projeto / Abstract: The competitive environment in which the companies who develop software tools for the design of integrated circuits creates many barriers to the establishment of standards and common platforms. Usually the need for several software tools leads to a design environment which is fragmented and difficult to manage. This work presents the development of software tool, based on graphical parametric user interfaces in TCL/TK, which integrates many general functions and allows for a quick codification of procedures and its access through the graphics elements. The developed tool optimizes and facilitates the tasks employed in the improvement of the techniques used in integrated circuits design through the elaboration of methods and scripts dedicated to the automation of the design flow steps / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica

L’objectif principal du projet est d’étudier les techniques d’analyses de défaillances des circuits intégrés VLSI basées sur l’emploi de laser. Les études ont été effectuées sur l’équipement à balayage laser MERIDIAN (DCGSystems) et le testeur Diamond D10 (Credence) disponible au CNES. Les travaux de thèse concernent l’amélioration des techniques dynamiques dites DLS comme « Dynamic Laser Stimulation ». Les techniques DLS consistent à perturber le fonctionnement d’un circuit intégré défaillant par effet photoélectrique ou effet photothermique, en fonctionnement dynamique, à l’aide d’un faisceau laser continu balayant la surface du circuit. Un faisceau laser modulé avec des impulsions supérieures à la nanoseconde et de façon synchrone avec le test électrique à l’aide d’un signal TTL peut être également avantageusement utilisé pour localiser des défauts non accessibles par des techniques purement statiques (OBIRCh, OBIC etc.). L’analyse de la réponse des paramètres électriques à la perturbation laser conduit à une identification de l’origine de la défaillance dynamique. L’optimisation des techniques DLS actuelles permet d’augmenter le taux de succès des analyses de défaillance et d’apporter des informations difficilement accessibles jusqu’alors, qui permettent la détermination de la cause racine de la défaillance.Dans un premier temps, le travail réalisé a consisté en l’amélioration du processus d’analyse des techniques DLS par l’intégration étroite avec le test de façon à observer tout paramètre électrique significatif lors du test DLS. Ainsi, les techniques de « Pass-Fail Mapping » ou encore les techniques paramétriques de localisation de défauts ont été implémentées sur le banc de test constitué du Meridian et du D10. La synchronisation du déroulement du test opéré par le testeur avec le balayage laser a permis par la suite d’établir des méthodologies visant à rajouter une information temporelle aux informations spatiales. En effet, en utilisant un laser modulé nous avons montré que nous étions capable d’identifier avec précision quels sont les vecteurs impliqués dans le comportement défaillant en modulant l’éclairement du faisceau laser en fonction de la partie de la séquence de test déroulée. Ainsi nous somme capable de corréler la fonction défaillante et les structures du CI impliquées. Cette technique utilisant le laser modulé est appelée F-DLS pour « Full Dynamic Laser Stimulation ». A l’inverse, nous pouvons connaitre la séquence de test qui pose problème, et par contre ne pas connaitre les structures du CI impliquées. Dans l’optique de rajouter cette l’information, il a été développé une technique de mesure de courant dynamique. Cette technique s’est avérée efficace pour obtenir des informations sur le comportement interne du CI. A titre d’exemple, prenons le cas des composants « latchés » où les signaux sont resynchronisés avant la sortie du composant. Il est difficile, même avec les techniques DLS actuelles, d’avoir des informations sur une dérive temporelle des signaux. Cependant l’activité interne du composant peut être caractérisée en suivant sur un oscilloscope l’évolution du courant lorsque le circuit est actif, sous la stimulation laser. L’information sur la dérive temporelle peut être extraite par observation de cette activité interne.Enfin, ces techniques de stimulation laser dynamique, ont également prouvé leur efficacité pour l’étude de la fiabilité des CI. La capacité de ces techniques à détecter en avance d’infimes variations des valeurs des paramètres opérationnels permet de mettre en évidence l’évolution des marges de ces paramètres lors d’un processus de vieillissement accéléré. L’étude de l’évolution de la robustesse des CI face aux perturbations externes est un atout majeur qu’apportent les techniques DLS à la fiabilité.Les méthodologies développées dans cette thèse, sont intégrées dans les processus d’analyse et de caractérisation de CI au laboratoire. / The principal objective of the project is to investigate laser based techniques for failure analysis of VLSI integrated circuits. The investigations will be performed on the DCGSystems’ Meridian laser scanning microscope coupled with the Credence’s Diamond D10 tester available at CNES. This study was interested more specifically in the improvement of dynamic laser stimulation techniques said DLS like Dynamic Laser Stimulation. DLS techniques consists in modifying the operation of a dynamically failing integrated circuit by photoelectric effect or photothermal effect using a continuous laser beam sweeping the surface of the circuit. A laser beam modulated in the nanosecond range synchronously with the electrical test through a TTL signal can also be advantageously used. Analysis of the electrical parameters response to the laser disturbance leads to an identification of the dynamic failure origin. The optimization of current DLS techniques will increase the failure analyses success rate and bring information hardly accessible by other means, which allows determining the failure root cause. The work performed was the improvement of the DLS process flow by closely integrating the test to monitor any relevant electrical parameters upon DLS. The « Pass-Fail Mapping » technique and the parametric techniques were implemented on the test tools combining the D10 and the Meridian. The synchronization of the test with the laser scan allows establishing methodologies and techniques in order to add timing information to the defect localisation. Indeed, by modulating the laser beam depending on the test pattern sequences, we show our capability to identify precisely which are the vectors responsible for the IC defective behaviour. We are able now to correlate the defective IC functions with the IC structures involved. This technique is known as F-DLS for Full Dynamic Laser Stimulation.In some cases, we know when the failure occurs in the test pattern but we ignore which IC structures are involved. So, we also developed a dynamic current measurement under laser stimulation technique. This technique proved to be efficient to obtain information about the internal IC behaviour. As an example, for the latched component which signals are synchronised just before the outputs, it is hard to measure shift in the signal propagation. Nevertheless, the IC internal activities can be characterized by monitoring on a scope the current variations under laser stimulation when the IC is activated. The information about the shift in the signal propagation could be extracted then by observing of the IC internal activities.Finally, these DLS techniques proved their efficiency for device qualification for reliability issues. Their accuracy allows early detection of operational parameter tiny variations. This is used to highlight electrical parameter margin evolutions during accelerated aging process. DLS techniques demonstrate their potential to deal with the IC robustness evolution facing external perturbation for reliability purposes.The techniques and methodologies developed during this work have been successfully integrated in the IC analysis and characterisation process in the laboratory. We exposed these techniques but the main case studies remain confidential.

Hall Effect integrated circuits are used in a wide range of applications to measure the strength and/or direction of magnetic fields. These sensors play an increasingly significant role in the fields of automation, medical treatment and detection thanks largely to the enormous development of information technologies and electronic industries. Commercial Hall Effect ICs available in the market are all based on silicon technology. These ICs have the advantages of low cost and compatibility with CMOS technology, but suffer from poor sensitivity and detectability, high power consumption and low operating frequency bandwidths. The objective of this work was to develop and fabricate the first fully monolithic GaAs-InGaAs-AlGaAs 2-Dimensional Electron Gas (2DEG) Hall Effect integrated circuits whose performance enhances pre-existing technologies. To fulfil this objective, initially 2 µm gate length pHEMTs and 60/20 µm (L/W) Greek cross Hall Effect sensors were fabricated on optimised GaAs-In.18Ga.82As-Al.35Ga.65As 2DEG structures (XMBE303) suitable for both sensor and integrated circuit designs. The pseudomorphic high electron mobility transistors (pHEMTs) produced state-of-the-art output conductance, providing high intrinsic gain of 405, current cut-off frequency of 4.8 GHz and a low negative threshold voltage of -0.4 V which assisted in designing single supply ICs with high sensitivity and wide dynamic range. These pHEMTs were then accurately modelled for use in the design and simulation of integrated circuits. The corresponding Hall sensor showed a current sensitivity of 0.4 mV/mA.mT and a maximum magnetic DC offset of 0.35 mT at 1 V. DC digital (unipolar) and DC linear Hall Effect integrated circuits were then designed, simulated, fabricated and fully characterised. The DC linear Hall Effect IC provided an overall sensitivity of 8 mV/mT and a power consumption as low as 6.35 mW which, in comparison with commercial Si DC linear Hall ICs, is at least a factor of 2 more power efficient. The DC digital (unipolar) Hall Effect IC demonstrated a switching sensitivity of 6 mT which was at least ~50% more sensitive compared to existing commercial unipolar Si Hall ICs. In addition, a novel low-power GaAs-InGaAs-AlGaAs 2DEG AC linear Hall Effect integrated circuit with unprecedented sensitivity and wide dynamic range was designed, simulated, fabricated and characterised. This IC provided a sensitivity of 533 nV/nT, minimum field detectability of 177 nT (in a 10 Hz bandwidth) at frequencies from 500 Hz up to 200 kHz, consuming only 10.4 mW of power from a single 5 V of supply. In comparison to commercial Si linear Hall ICs, this IC provides an order of magnitude larger sensitivity, a factor of 4 higher detectability, 20 times wider bandwidth and over 20% lower power consumption (10.4 mW vs. 12.5 mW). These represent the first reported monolithic integrated circuits using a CMOS-like technology but in GaAs 2DEG technology and are extremely promising as complements, if not alternatives, to CMOS Si devices in high performance applications (such as high temperatures operations (>150 °C) and radiation hardened environment in the nuclear industry).

This design covers the design of an integrated circuit (IC) in support of the active contact lens project at Cal Poly. The project aims to monitor intraocular eye pressure (IOP) to help diagnose and treat glaucoma, which is expected affect 6.3 million Americans by 2050. The IC is designed using IBM’s 130 nm 8RF process, is powered by an on-lens thin film 3.8 V rechargeable battery, and will be fabricated at no cost through MOSIS. The IC features a low-power linear regulator that powers a current-starved voltage-controlled oscillator (CSVCO) used for establishing a backscatter communication link. Additional circuitry is included to regulate power to and from the battery. An undervoltage lockout circuit protects the battery from deep discharge damage. When recharging, a rectifier and a voltage regulator provides overvoltage protection. These circuit blocks are biased primarily using a 696 mV subthreshold voltage reference that consumes 110.5 nA.

The main goal of this diploma thesis is to compare two circuits designed for LED powering with output current of units of Amperes. Both circuits are based on step-down converter topology, one with technology of synchronous rectifying and the other one without it. Calculations and selection of used components with real prototypes were made for both selected circuits. All selected components meet automotive qualification requirements for discrete products. Produced prototypes were compared in terms of functionality, efficiency, EMC and thermal radiation.