Advances in technology and the introduction of high speed processors have increased the demand for fast, compact and commercial methods for transferring large amounts of data. The next generation of the communication access network will use optical fiber as a media for data transmission to the subscriber. In optical data or chip-to-chip data communication, the continuous received data needs to be converted to discrete data. For the conversion, a synchronous clock and data are required. A clock and data recovery (CDR) circuit recovers the phase information from the data and generates the in-phase clock and data. In this dissertation, two clock and data recovery circuits for Giga-bits per second (Gbps) serial data communication are designed and fabricated in 180nm and 90nm CMOS technology. The primary objective was to reduce the circuit power dissipation for multi-channel data communication applications. The power saving is achieved using low swing voltage signaling scheme. Furthermore, a novel low input swing Alexander phase detector is introduced. The proposed phase detector reduces the power consumption at the transmitter and receiver blocks. The circuit demonstrates a low power dissipation of 340µW/Gbps in 90nm CMOS technology. The CDR is able to recover the input signal swing of 35mVp. The peak-to-peak jitter is 21ps and RMS jitter is 2.5ps. Total core area excluding pads is approximately 0.01mm2.

Advances in technology and the introduction of high speed processors have increased the demand for fast, compact and commercial methods for transferring large amounts of data. The next generation of the communication access network will use optical fiber as a media for data transmission to the subscriber. In optical data or chip-to-chip data communication, the continuous received data needs to be converted to discrete data. For the conversion, a synchronous clock and data are required. A clock and data recovery (CDR) circuit recovers the phase information from the data and generates the in-phase clock and data. In this dissertation, two clock and data recovery circuits for Giga-bits per second (Gbps) serial data communication are designed and fabricated in 180nm and 90nm CMOS technology. The primary objective was to reduce the circuit power dissipation for multi-channel data communication applications. The power saving is achieved using low swing voltage signaling scheme. Furthermore, a novel low input swing Alexander phase detector is introduced. The proposed phase detector reduces the power consumption at the transmitter and receiver blocks. The circuit demonstrates a low power dissipation of 340µW/Gbps in 90nm CMOS technology. The CDR is able to recover the input signal swing of 35mVp. The peak-to-peak jitter is 21ps and RMS jitter is 2.5ps. Total core area excluding pads is approximately 0.01mm2.

Optical interconnects are important to the future development of microelectronics. Volume grating couplers (VGCs) provide a compact, efficient coupling mechanism that is compatible with microelectronics fabrication processes. In this dissertation, some of the performance characteristics of VGCs are investigated. Also, integration of VGCs with Sea of Polymer Pillars (SoPP), an emerging high-density input/output interconnect technology, is demonstrated and its performance quantitatively investigated. First, the polarization-dependent performance of VGCs is analyzed, and the design constraints for achieving high-efficiency polarization-dependent and polarization-independent VGCs are examined. The effects of loss on VGC performance are also presented. Then, the wavelength response of VGCs and its dependence on grating parameters is quantitatively examined. Experimental demonstrations of polarization-dependent and polarization-independent VGCs are then presented. Finally, a VGC integrated with a SoPP is demonstrated and its performance characterized.

As the complexity of interconnects and packages increases and the rise and fall time of the signal decreases, the electromagnetic effects of distributed passive devices are becoming an important factor in determining the performance of gigahertz systems. The electromagnetic behavior extracted using an electromagnetic simulation or from measurements is available as frequency dependent data. This information can be represented as a black box called a macromodel, which captures the behavior of the passive structure at the input/output ports. In this dissertation, the macromodels have been categorized as scalable, passive and broadband macromodels. The scalable macromodels for building design libraries of passive devices have been constructed using multidimensional rational functions, orthogonal polynomials and selective sampling. The passive macromodels for time-domain simulation have been constructed using filter theory and multiport passivity formulae. The broadband macromodels for high-speed simulation have been constructed using band division, selector, subband reordering, subband dilation and pole replacement. An automated construction method has been developed. The construction time of the multiport macromodel has been reduced. A method for reducing the order of the macromodel has been developed. The efficiency of the methods was demonstrated through embedded passive devices, known transfer functions and distributed interconnect networks.

Switching power converters are an indispensable part of every battery-operated consumer electronic product, nourishing regulated voltages to various subsystems. In these circuits, sensing the inductor current is not only necessary for protection and control but also is critical to be done in a lossless and accurate fashion for state-of-the-art advanced control techniques, which are devised to optimize transient response, increase the efficiency over a wide range of loads, eliminate off-chip compensation networks, and integrate the power inductor. However, unavailability of a universal, integrable, lossless, and accurate current-sensing technique impedes the realization of those advanced techniques and limit their applications. Unfortunately, use of a conventional series sense resistor is not recommended in high-performance, high-power switching regulators where more than 90% efficiency is required because of their high current levels. A handful of lossless current-sensing techniques are available but their accuracies are significantly lower than the traditional sense resistor scheme. Among available lossless but not accurate techniques, an off-chip, filter-based method that uses a tuned filter across the inductor to estimate current flow and its accuracy is dependent on the inductance and its equivalent series resistance (ESR) was selected for improvement because of its inherent continuous and low-noise operation. A schemes is proposed to adapt the filter technique for integration by automatically adjusting bandwidth and gain of an on-chip programmable gm-C filter to the off-chip power inductor during the system start-up through measuring the inductance and its ESR with on-chip generated test currents. The IC prototype in AMI s 0.5-um CMOS process achieved overall DC and AC gain errors of 8% and 9%, respectively, at 0.8 A DC load and 0.2 A ripple currents for inductors from 4 uH-14 uH and ESR from 48 mOhm to 384 mOhm when lossless, state-of-the-art schemes achieve 20 40% error and only when the nominal specifications of power component (power MOSFET or inductor) are known. Moreover, the proposed circuit improved the efficiency of a test bed current-mode controlled switching regulator by more than 2.6% at 0.8 A load compared to the traditional sense resistor technique with a 50 mOhm sense resistor.

Low size, low power, and wearable bio-signal recording systems require acquisition front-ends with high common-mode rejection for interference suppression and adjustable gain to provide an optimum signal level to a cascading analog-to-digital stage. This thesis presents the realization of microcontroller operated double-differential (DD) recording setup with automatic gain control (AGC) and automatic balance control, which can adjust the magnitude of recorded bio-potential signal to a target level and reject common-mode interference for full-bandwidth recording without filtering. Microcontroller code realizes the automatic control method of gain and balance adjustment by detecting, computing, and varying parameters to set timing clock pulses, which determine the gain magnitude and balance state. The automatic balance control compensates for imbalance in electrode interface impedance. The double-differential amplifier is implemented using two integrated variable gain amplifiers (ASIC) and one adder. Measured results of the variable gain amplifiers fabricated in 0.35 £gm CMOS technology show an input spot noise of 169 nV/¡ÔHz, a NEF below 10, and a circuit active area of 0.017 mm2 with a power consumption of 1.44 £gW. Measured results of the double-differential amplifier setup confirm interference suppression of 25.7 dB, tunable gain range of 39.6 dB, and 239 nV/¡ÔHz noise assuming ¡Ó10% interface mismatch. Practical measured examples incorporating the chips confirm gain control suitable for bio-potential recording and interference suppression in a balanced DD arrangement for electrocardiogram and electromyogram recording.

This thesis researchs the design of quadrature modulator consists of 120MHz quadrature modulator that is fabricated using hybrid elements and print circuit board (PCB) technology for digital signal generator and quadrature modulator monolithic-microwave integrated-circuit (MMIC) that is fabricated using GaAs heterojunction bipolar transistor (HBT) technology for Personal Communication Service (PCS) applications. The 120MHz quadrature modulator incorporates power divider/combiner, phase shifter and doubly balanced mixer; the design architecture, principle and measurement results of division are presented in this thesis. A quadrature modulator is implemented by combining every division and measures specifications accurately, comparing with that of Agilent ESG-D series digital signal generator with the same carrier frequency and digital modulation. The quadrature modulator MMIC for PCS applications incorporates phase shifter, Gilbert cell mixer, differential to single-ended converter and RF amplifier at output; the design architecture, principle and simulation results of division are presented in this thesis. A quadrature modulator is integrated by combining every division and simulates parameters strictly.For troublesome specification measurement of quadrature modulator, this thesis also presents measurement method and instrument setup detailedly.

Asian countries imitate the success of Taiwan IC industry, especially Mainland China. Therefore, it is compared between Mainland China and Taiwan to discover the differences and similarities in my thesis. National innovation systems are divided into national industry innovation policies and industrial innovation systems; the former is composed of the history of IC industry, technical policies and industrial policies. And the latter is composed of the resources of technical people, industrial gatherings, research institutions, technical resource and transference. Finally, there are three points in my conclusion. First, the use of industrial policies and the portal model of foreign businessmen are similar. But they, for instance, the period of IC technology enlightenment, the early timing and importance of technology policies, the used way of industry policy, the way of technological transference, scientific research institutions and the local Fabs, are different. Second, their IC design industry is driven by Foundry. It occurs the special division of industry. And the development of their IC industry is driven by demand market in itself. The last, many 8 inches Fabs are built.

This study uses the spatial features of defects on the wafers to examine the detection and control of process variation in semiconductor fabrication. It applies spatial stochastic process to semiconductor yield modeling and the extrinsic reliabil- ity estimation model. New yield models of integrated circuits based on the spatial point process are established. The defect density which varies according to location on the wafer is modeled by the spatial nonhomogeneous Poisson process. And, in order to capture the variations in defect patterns between wafers, a random coeff- cient model and model-based clustering are applied. Model-based clustering is also applied to the fabrication process control for detecting these defect clusters that are generated by assignable causes. An extrinsic reliability model using defect data and a statistical defect growth model are developed based on the new yield model.

Although copper (Cu) is the preferred interconnect material due to its lower resistivity than aluminum (Al), Cu subtractive etching processes have not been developed at temperatures less than 180 °C, primarily due to the inability to form volatile etch products at low temperature. The conventional damascene technology avoids the need for subtractive etching of Cu by electroplating Cu into previously etched dielectric trenches/vias, followed by a chemical/mechanical planarization (CMP) process. However, a critical "size effect" limitation has arisen for damascene technology as a result of the continuing efforts to adhere to "Moore's Law". The size effect relates to the fact that the resistivity of damascene-generated lines increases dramatically as the line width approaches the sub-100 nm regime, where feature size is similar to the mean free path of electrons in Cu (40 nm). As a result, an alternative Cu patterning process to that of damascene may offer advantages for device speed and thus operation. This thesis describes investigations into the development of novel, fully-plasma based etch processes for Cu at low temperatures (10 °C). Initially, the investigation of a two-step etch process has been studied. This etch approach was based on a previous thermodynamic analysis of the Cu-Cl-H system by investigators at the University of Florida. In the first step, Cu films are exposed to a Cl₂ plasma to preferentially form CuCl₂, which is believed to be volatilized as Cu₃Cl₃ by subsequent exposure to a hydrogen (H₂) plasma (second step). Patterning of Cu films masked with silicon dioxide (SiO₂) layers in an inductively coupled plasma (ICP) reactor indicates that the H₂ plasma step in the two-step process is the limiting step in the etch process. This discovery led to the investigation of a single step Cu etch process using a pure H₂ plasma. Etching of blanket Cu films and Cu film patterning at 10°C, display an etch rate ~ 13 nm/min; anisotropic etched features are also observed. Comparison of H₂ plasma etching to sputtering of Cu films in argon (Ar) plasmas, indicates that both a chemical component and a physical component are involved in the etching mechanism. Additional studies using helium plasmas and variation of power applied to the plasma and etching surface demonstrate that the etch rate is controlled by reactive hydrogen species, ion bombardment flux and likely photon flux. Optical Emission Spectroscopy (OES) of the H₂ plasma during the Cu etching process detects Cu emission lines, but is unable to identify specific Cu etch products that desorb from the etching surface. Variation of Cu etch rates as a function of temperature suggests a change in mechanism for the removal of Cu over the temperature of -150 °C to 150 °C. OES analyses also suggest that the Cl₂ plasma step in the two-step process can inhibit Cu etching, since the subsequent H₂ (second) plasma step shows a time delay in film removal. Preliminary results of the etching of the SiO₂ mask material in H₂ plasmas with various intentionally introduced contaminants demonstrate the robustness of the H₂ plasma Cu etch process.